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EPM9320A Datasheet(PDF) 6 Page - Altera Corporation |
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EPM9320A Datasheet(HTML) 6 Page - Altera Corporation |
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6 / 46 page  6 Altera Corporation MAX 9000 Programmable Logic Device Family Data Sheet Figure 1. MAX 9000 Device Block Diagram Logic Array Blocks The MAX 9000 architecture is based on linking high-performance, flexible logic array modules called logic array blocks (LABs). LABs consist of 16-macrocell arrays that are fed by the LAB local array, as shown in Figure 2 on page 7. Multiple LABs are linked together via the FastTrack Interconnect, a series of fast, continuous channels that run the entire length and width of the device. The I/O pins are supported by I/O cells (IOCs) located at the end of each row (horizontal) and column (vertical) path of the FastTrack Interconnect. Each LAB is fed by 33 inputs from the row interconnect and 16 feedback signals from the macrocells within the LAB. All of these signals are available within the LAB in their true and inverted form. In addition, 16 shared expander product terms (“expanders”) are available in their inverted form, for a total of 114 signals that feed each product term in the LAB. Each LAB is also fed by two low-skew global clocks and one global clear that can be used for register control signals in all 16 macrocells. IOC IOC IOC IOC IOC IOC IOC IOC IOC IOC IOC IOC IOC IOC I/O Cell (IOC) Logic Array Block (LAB) Macrocell FastTrack Interconnect IOC IOC LAB Local Array |
Similar Part No. - EPM9320A |
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Similar Description - EPM9320A |
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