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EL7532IY Datasheet(PDF) 8 Page - Intersil Corporation |
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EL7532IY Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 8 page 8 FN7435.5 August 12, 2005 At extreme conditions (VIN < 3V, IO > 0.7A, and junction temperature higher than 75°C), input cap C1 is recommended to be 22µF. Otherwise, if any of the above 3 conditions is not true, C1 can remain as low as 10µF. The RMS current present at the input capacitor is decided by the following formula: This is about half of the output current IO for all the VO. This input capacitor must be able to handle this current. The inductor peak-to-peak ripple current is given as: • L is the inductance •fS the switching frequency (nominally 1.5MHz) The inductor must be able to handle IO for the RMS load current, and to assure that the inductor is reliable, it must handle the 3A surge current that can occur during a current limit condition. Current Limit and Short-Circuit Protection The current limit is set at about 3A for the PMOS. When a short-circuit occurs in the load, the preset current limit restricts the amount of current available to the output, which causes the output voltage to drop below the preset voltage. In the meantime, the excessive current heats up the regulator until it reaches the thermal shut-down point. Thermal Shut-Down Once the junction reaches about 145°C, the regulator shuts down. Both the P channel and the N channel MOSFETs turn off. The output voltage will drop to zero. With the output MOSFETs turned off, the regulator will soon cool down. Once the junction temperature drops to about 130°C, the regulator will restart again in the same manner as the EN pin connects to logic HI. Thermal Performance The EL7532 is in a fused-lead MSOP10 package. Compared to the regular MSOP10 package, the fused-lead package provides lower thermal resistance. The typical θJA of 115°C/W (See Thermal Information section in spec table) can be improved by maximizing the copper area around the pins. A θJA of 100°C/W can be achieved on a 4-layer board and 125°C/W on a 2-layer board. Refer to Intersil’s Tech Brief, TB379, for more information on thermal resistance. Layout Considerations The layout is very important for the converter to function properly. The following PC layout guidelines should be followed: • Separate the Power Ground ( ) and Signal Ground ( ); connect them only at one point right at the pins • Place the input capacitor as close to VIN and PGND pins as possible • Make the following PC traces as small as possible: - from LX pin to L - from CO to PGND • If used, connect the trace from the FB pin to R1 and R2 as close as possible • Maximize the copper area around the PGND pin • Place several via holes under the chip to additional ground plane to improve heat dissipation The demo board is a good example of layout based on this outline. Please refer to the EL7532 Application Brief. IINRMS VO VIN - VO () × VIN ------------------------------------------------ IO × = ∆I IL VIN ( - VO) VO × LVIN fS × × -------------------------------------------- = EL7532 |
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