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ISL6615CRZ Datasheet(PDF) 6 Page - Intersil Corporation |
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ISL6615CRZ Datasheet(HTML) 6 Page - Intersil Corporation |
6 / 11 page 6 FN6481.0 April 24, 2008 Description Operation Designed for versatility and speed, the ISL6615 MOSFET driver controls both high-side and low-side N-Channel FETs of a half-bridge power train from one externally provided PWM signal. Prior to VCC exceeding its POR level, the Pre-POR overvoltage protection function is activated during initial start-up; the upper gate (UGATE) is held low and the lower gate (LGATE), controlled by the Pre-POR overvoltage protection circuits, is connected to the PHASE. Once the VCC voltage surpasses the VCC Rising Threshold (see “Electrical Specifications” on page 4), the PWM signal takes control of gate transitions. A rising edge on PWM initiates the turn-off of the lower MOSFET (see Figure 1). After a short propagation delay [tPDLL], the lower gate begins to fall. Typical fall times [tFL] are provided in the “Electrical Specifications” on page 4. Adaptive shoot-through circuitry monitors the LGATE voltage and determines the upper gate delay time [tPDHU]. This prevents both the lower and upper MOSFETs from conducting simultaneously. Once this delay period is complete, the upper gate drive begins to rise [tRU] and the upper MOSFET turns on. A falling transition on PWM results in the turn-off of the upper MOSFET and the turn-on of the lower MOSFET. A short propagation delay [tPDLU] is encountered before the upper gate begins to fall [tFU]. Again, the adaptive shoot-through circuitry determines the lower gate delay time, tPDHL. The PHASE voltage and the UGATE voltage are monitored, and the lower gate is allowed to rise after PHASE drops below a level or the voltage of UGATE to PHASE reaches a level depending upon the current direction (see the following section titled “Advanced Adaptive Zero Shoot-through Dead-time Control” for details). The lower gate then rises [tRL], turning on the lower MOSFET. Advanced Adaptive Zero Shoot-through Dead-time Control The ISL6615 driver incorporates a unique adaptive dead-time control technique to minimize dead-time, resulting in high efficiency from the reduced freewheeling time of the lower MOSFETs’ body-diode conduction, and to prevent the upper and lower MOSFETs from conducting simultaneously. This is accomplished by ensuring the rising gate turns on its MOSFET with minimum and sufficient delay after the other has turned off. During turn-off of the lower MOSFET, the LGATE voltage is monitored until it drops below 1.75V. Prior to reaching this level, there is a 25ns blanking period to protect against sudden dips in the LGATE voltage. Once 1.75V is reached the UGATE is released to rise after 20ns of propagation delay. Once the PHASE is high, the adaptive shoot-through circuitry monitors the PHASE and UGATE voltages during PWM falling edge and subsequent UGATE turn-off. If PHASE falls to less than +0.8V, the LGATE is released to turn on after 10ns of propagation delay. If the UGATE-PHASE falls to less than 1.75V and after 40ns of propagation delay, LGATE is released to rise. Tri-state PWM Input A unique feature of these drivers and other Intersil drivers is the addition of a shutdown window to the PWM input. If the PWM signal enters and remains within the shutdown window for a set holdoff time, the driver outputs are disabled and both MOSFET gates are pulled and held low. The shutdown state is removed when the PWM signal moves outside the shutdown window. Otherwise, the PWM rising and falling thresholds outlined in the “Electrical Specifications” on page 4 determine when the lower and upper gates are enabled. This feature helps prevent a negative transient on the output voltage when the output is shut down, eliminating the PWM UGATE LGATE tFL tPDHU tPDLL tRL tTSSHD tPDTS tPDTS 1.18V < PWM < 2.36V 0.76V < PWM < 1.96V tFU tRU tPDLU tPDHL tTSSHD FIGURE 1. TIMING DIAGRAM ISL6615 |
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