8

FN6601.2

March 19, 2009

The total gate drive power losses are dissipated among the

resistive components along the transition path, as outlined in

Equation 4. The drive resistance dissipates a portion of the

total gate drive power losses, the rest will be dissipated by the

the typical upper and lower gate drives turn-on current path.

Application Information

Layout Considerations

During switching of the devices, the parasitic inductances of

the PCB and the power devices’ packaging (both upper and

lower MOSFETs) leads to ringing, possibly in excess of the

absolute maximum rating of the devices. Careful layout can

help minimize such unwanted stress. The following advice is

meant to lead to an optimized layout:

• Keep decoupling loops (LVCC-GND and BOOT-PHASE)

as short as possible.

• Minimize trace inductance, especially low-impedance

lines: all power traces (UGATE, PHASE, LGATE, GND,

LVCC) should be short and wide, as much as possible.

• Minimize the inductance of the PHASE node: ideally, the

source of the upper and the drain of the lower MOSFET

should be as close as thermally allowable.

• Minimize the input current loop: connect the source of the

lower MOSFET to ground as close to the transistor pin as

feasible; input capacitors (especially ceramic decoupling)

should be placed as close to the drain of upper and source

of lower MOSFETs as possible.

In addition, for improved heat dissipation, place copper

underneath the IC whether it has an exposed pad or not. The

copper area can be extended beyond the bottom area of the

IC and/or connected to buried power ground plane(s) with

thermal vias. This combination of vias for vertical heat

escape, extended surface copper islands, and buried planes

combine to allow the IC and the power switches to achieve

their full thermal potential.

Upper MOSFET Self Turn-On Effects At Startup

Should the driver have insufficient bias voltage applied, its

outputs are floating. If the input bus is energized at a high

dV/dt rate while the driver outputs are floating, due to

the upper MOSFET could momentarily rise up to a level

greater than the threshold voltage of the device, potentially

turning on the upper switch. Therefore, if such a situation

could conceivably be encountered, it is a common practice to

upper MOSFET to suppress the Miller coupling effect. The

value of the resistor depends mainly on the input voltage’s

threshold of the upper MOSFET. A higher dV/dt, a lower

will require a smaller resistor to diminish the effect of the

internal capacitive coupling. For most applications, the

integrated 20k

Ω resistor is sufficient, not affecting normal

performance and efficiency.

The coupling effect can be roughly estimated with

Equation 5, which assumes a fixed linear input ramp and

neglects the clamping effect of the body diode of the upper

drive and the bootstrap capacitor. Other parasitic

components such as lead inductances and PCB

capacitances, are also not taken into account. Figure 5

provides a visual reference for this phenomenon and its

potential solution.

FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH

FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH

P

DR

P

DR_UP

P

DR_LOW

I

Q

VCC

•

++

=

(EQ. 4)

P

DR_UP

R

HI1

R

HI1

R

EXT1

+

--------------------------------------

R

LO1

R

LO1

R

EXT1

+

----------------------------------------

+

⎝⎠

⎜⎟

⎛⎞ P

Qg_Q1

2

---------------------

•

=

P

DR_LOW

R

HI2

R

HI2

R

EXT2

+

--------------------------------------

R

LO2

R

LO2

R

EXT2

+

----------------------------------------

+

⎝⎠

⎜⎟

⎛⎞ P

Qg_Q2

2

---------------------

•

=

R

EXT1

R

G1

R

GI1

N

Q1

-------------

+

=

R

EXT2

R

G2

R

GI2

N

Q2

-------------

+

=

Q1

D

S

G

BOOT

PHASE

UVCC

LVCC

Q2

D

S

G

V

GS_MILLER

dV

dt

------- RC

V

–

DS

dV

dt

------- RC

⋅

iss

⋅

----------------------------------

–

⎝⎠

⎜⎟

⎜⎟

⎜⎟

⎜⎟

⎛⎞

⋅⋅

=

RR

UGPH

R

GI

+

=

C

rss

C

GD

=

C

iss

C

GD

C

GS

+

=

(EQ. 5)

ISL6622A