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EL9200 Datasheet(PDF) 10 Page - Intersil Corporation |
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EL9200 Datasheet(HTML) 10 Page - Intersil Corporation |
10 / 15 page 10 FN7438.1 October 30, 2008 Application Information This device provides the ability to reduce the flicker of an LCD panel by adjustment of the VCOM voltage during production test and alignment. A 128-step resolution is provided under digital control which adjusts the sink current of the output. The output is connected to an external voltage divider, so that the device will have the capability to reduce the voltage on the output by increasing the output sink current. The adjustment of the output and the programming of the non-volatile memory are provided on one pin while the counter enable (CE) is provided on a separate pin. The output is adjusted via the CTL pin either by counting up with a mid to low transition or by counting down with a mid to high transition. Once the minimum or maximum value is reached on the 128 steps, the device will not overflow or underflow beyond that minimum or maximum value. An increment of the counter will increase the output sink current which will lower the voltage on the external voltage divider. A decrement of the counter will decrease the output sink current, which will raise the voltage on the external voltage divider. Once the desired output level is obtained, the part can store it's setting using the non-volatile memory in the device. See the “Non-Volatile Memory (EEPROM) Programming” on page 12 for detailed information. Note: Once the desired output level is stored in the EEPROM, the CE pin must go low to preserve the stored value. Adjustable Sink Current Output The device provides an output sink current which lowers the voltage on the external voltage divider. The equations that control the output are given in Equation 1: NOTE: Where setting is an integer between 1 and 128. 7-Bit Up/Down Counter The counter sets the level to the digital potentiometer and is connected to the non-volatile memory. When the part is programmed, the counter setting is loaded into the non-volatile memory. This value will be loaded from the non-volatile memory into the counter during power-on. The counter will not exceed its maximum level and will hold that value during subsequent increment requests on the CTL pin. The counter will not exceed its minimum level and will hold that value during subsequent decrement requests on the CTL pin. CTL Pin CTL should have a noise filter to reduce bouncing or noise on the input that could cause unwanted counting when the CE pin is high. The board should have an additional ESD protection circuit, with a series 1k Ω resistor and a shunt 0.01µF capacitor connected on the CTL pin. In order to increment the setting, pulse CTL low for more than 200µs. The output sink current increases and lowers the VCOM lever by one least-significant bit (LSB). On the other hand, to decrement the setting, pulse CTL high for FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Amplifier Typical Performance Curves (Continued) JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 3.378W θ JA = 37 °C /W QF N2 4 0 150 AMBIENT TEMPERATURE (°C) 75 4.5 3.0 0 1.0 4.0 2.0 2.5 0.5 3.5 1.5 25 100 50 125 85 JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD θ JA = 14 0°C /W QF N2 4 893mW 0 150 AMBIENT TEMPERATURE (°C) 75 1.2 0.6 0 1.0 0.2 0.4 0.8 25 100 50 125 85 I OUT Setting 128 --------------------- A VDD 20 R SET () --------------------------- × = V OUT R 2 R 1 R 2 + --------------------- ⎝⎠ ⎜⎟ ⎛⎞ V AVDD 1 Setting 128 --------------------- R 1 20 R SET () --------------------------- × – ⎝⎠ ⎜⎟ ⎛⎞ = (EQ. 1) EL9200, EL9201, EL9202 |
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Similar Description - EL9200 |
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