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ISL6622BIRZ Datasheet(PDF) 7 Page - Intersil Corporation |
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ISL6622BIRZ Datasheet(HTML) 7 Page - Intersil Corporation |
7 / 11 page 7 March 19, 2009 down to a lower drive voltage with GVOT can improve the switching losses seen and maximize system efficiency. Figure 2 shows that the gate drive voltage optimization is accomplished via an internal low drop out regulator (LDO) that regulates the lower gate drive voltage. LVCC is driven to a lower voltage depending on the GD_SEL pin impedance. The input and output of this internal regulator are the VCC and LVCC pins, respectively. Both VCC and LVCC should be decoupled with a high quality, low ESR ceramic capacitor. In the 8 Ld SOIC package, the ISL6622B drives the upper gate to 12V while the lower drive voltage is fixed at 5.75V. The 10 Ld DFN part offers more flexibility: the upper gate can be driven from 5V to 12V via the UVCC pin, while the lower gate has a resistor-selectable drive voltage of 5.75V, 6.75V, and 7.75V (typically). This provides the flexibility necessary to optimize applications involving trade-offs between gate charge and conduction losses. Table 1 shows the LDO output (LVCC) level set by GD_SEL pin impedance. Figure 3 illustrates the internal LDO’s variation with the average load current plotted over a range of temperatures spanning from -40°C to +120°C. Should finer tweaking of this LVCC voltage be necessary, a resistor (RCC) can be used to shunt the LDO, as shown in Figure 2. The resistor thus delivers part of the LGATE drive current, leaving less current going through the internal LDO, elevating the LDO’s output voltage. Further reduction in RCC’s value can raise the LVCC voltage further, as desired. Power-On Reset (POR) Function During initial start-up, the VCC voltage rise is monitored. Once the rising VCC voltage exceeds the rising POR threshold, operation of the driver is enabled and the PWM input signal takes control of the gate drives. If VCC drops below the POR falling threshold, operation of the driver is disabled. Pre-POR Overvoltage Protection While VCC is below its POR level, the upper gate is held low and LGATE is connected to the PHASE pin via an internal 10k Ω (typically) resistor. By connecting the PHASE node to the gate of the low side MOSFET, the driver offers some passive protection to the load if the upper MOSFET(s) is or becomes shorted. If the PHASE node goes higher than the gate threshold of the lower MOSFET, it results in the progressive turn-on of the device and the effective clamping of the PHASE node’s rise. The actual PHASE node clamping level depends on the lower MOSFET’s electrical characteristics, as well as the characteristics of the input supply and the path connecting it to the respective PHASE node. Internal Bootstrap Device The ISL6622B features an internal bootstrap Schottky diode. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. The bootstrap function is also designed to prevent the bootstrap capacitor from overcharging due to the large negative swing at the trailing-edge of the PHASE node. This reduces the voltage stress on the BOOT to PHASE pins. The bootstrap capacitor must have a maximum voltage rating well above the maximum voltage intended for UVCC. Its minimum capacitance value can be estimated from Equation 1: where QG1 is the amount of gate charge per upper MOSFET at VGS1 gate-source voltage and NQ1 is the number of control MOSFETs. The ΔV BOOT_CAP term is defined as the allowable droop in the rail of the upper gate drive. Select results are exemplified in Figure 4. TABLE 1. LDO OPERATION AND OPTIONS PWM INPUT GD_SEL PIN LVCC @ 50mA DC LOAD Don’t Care Floating 5.75V (Typical; Fixed in SOIC Package) 4.5k Ω to GND 6.75V(Typical) GND 7.75V(Typical) FIGURE 2. GATE VOLTAGE OPTIMIZATION (GVOT) DETAIL EXTERNAL CIRCUIT ISL6622B INTERNAL CIRCUIT VIN VCC LVCC 1µF 1µF SET BY GD_SEL GVOT LDO RCC = OPTION FOR HIGHER LVCC RCC THAN PRE-SET BY GD_SEL + - + - > LGATE DRIVER 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 0 20406080 100 AVERAGE LOAD CURRENT (mA) FIGURE 3. TYPICAL LVCC VARIATION WITH LOAD GD_SEL TIED TO GND GD_SEL TIED TO 4.5k Ω TO GND GD_SEL FLOATING +120°C +40°C -40°C C BOOT_CAP Q GATE ΔV BOOT_CAP -------------------------------------- ≥ Q GATE Q G1 UVCC • V GS1 ------------------------------------ N Q1 • = (EQ. 1) ISL6622B |
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