ISL6217

8

V

CC-CORE

VID

VR_ON / EN

PGOOD

Vccp / Vcc_mch

PGOOD

Vcc_core

>10us

t2

3ms to 12ms

V

BOOT

V

VID

< 3ms

-12%

Capture VID Code

t1

FIGURE 2.

TIMING DIAGRAM SHOWING VR_ON, VCC_CORE AND PGOOD FOR VCC_CORE, VCCP AND VCC_MCH

Operation

Initialization

Once the +5VDC supply voltage, as connected to the

ISL6217 VDD pin, reaches the Power-On Reset (POR)

rising threshold, the PWM drive signals are held in “high-

impedance state” or high impedance mode. This results in

both high and low side MOSFETs being held low. Once the

supply voltage exceeds the POR rising threshold, the

controller will respond to a logic level high on the EN pin

and initiate the soft-start interval. If the supply voltage

drops below the POR falling threshold, POR shutdown is

triggered and the PWM signals are again driven to “high-

impedance state”.

The system signal, VR_ON is directly connected to the EN

pin of the ISL6217. Once the voltage on the EN pin rises

above 2.0V, the chip is enabled and soft-start begins. The

EN pin of the ISL6217 is also used to reset the ISL6217, for

cases when an undervoltage or overcurrent fault condition

has latched the IC off. A toggling of the state of this pin to a

level below 1.0V will re-enable the IC. For the case of an

overvoltage fault, the VDD pin must be reset.

During start-up, the ISL6217 regulates to the voltage on the

STV pin. This is referred to as the “Boot” voltage and is

labeled VBOOT in Figure 2. Once power good signals are

received from the Vccp and Vcc_mch regulators, the

ISL6217 will capture the VID code and regulate to this

command voltage within 3ms to 12ms. The PGOOD pin of

the ISL6217 is both an input and an output and is further

described in the “Fault Protection” section of this document.

Soft-Start Interval

Once VDD rises above the POR rising threshold and the

EN pin voltage is above the threshold of 2.0V, a soft-start

interval is initiated (Refer to Figures 2 and 3).

The voltage on the EA+ pin is the reference voltage for the

regulator. The voltage on the EA+ pin is equal to the

voltage on the SOFT pin minus the “Droop” resistor

voltage, VDROOP. During start-up, when the voltage on

SOFT is less than the “Boot” voltage VBOOT, a small 30µA

current source, I1, is used to slowly ramp up the voltage on

the soft-start Capacitor CSOFT. This slowly ramps up the

reference voltage for the controller, and therefore, controls

the slew rate of the output voltage. The STV pin is

externally programmable and sets the start-up, or “Boot”

voltage, VBOOT. The programming of this voltage level is

explained in the “STV, DSV and DRSV” section of this

document.

The ISL6217 PGOOD pin is both an input and an output.

The system signal, IMVP4_PWRGD, is connected to power

good signals from the Vccp and Vcc_mch supplies. The

Intersil ISL6227, Dual Voltage Regulator is an ideal choice

for the Vccp and Vcc_mch supplies.

Once the output voltage is within the “Boot” level regulation

limits and a logic high PGOOD signal from the Vccp and

Vccp_mch regulators is received, the ISL6217 is enabled to

capture the VID code and regulate to that command

voltage (Refer to Figure 2 and Figure 3). A second current

source, I2, is added to I1, after the initial start-up transition.

I2 is approximately 100µA, and raises the total SOFT pin

sinking and sourcing current to 130µA. This increased

current is used to increase the slew rate of the reference to

meet all Active, Deep and Deeper Sleep slew rate

requirements of the Intel IMVP-IV™ and IMVP-IV+™

specification.