6

FN6618.0

December 14, 2007

START Condition Setup Time

SCL rising edge to SDA

falling edge. Both crossing

600

ns

START Condition Hold Time

From SDA falling edge

falling edge crossing 70% of

600

ns

Input Data Setup Time

From SDA exiting the 30% to

rising edge crossing 30% of

100

ns

Input Data Hold Time

From SCL falling edge

entering the 30% to 70% of

0

900

ns

STOP Condition Setup Time

From SCL rising edge

rising edge crossing 30% of

600

ns

STOP Condition Hold Time

From SDA rising edge to

SCL falling edge. Both

600

ns

Output Data Hold Time

From SCL falling edge

SDA enters the 30% to 70%

0ns

SDA and SCL Rise Time

20 + 0.1 x Cb

300

ns

7, 9

SDA and SCL Fall Time

20 + 0.1 x Cb

300

ns

7, 9

Cb

Capacitive loading of SDA or SCL

Total on-chip and off-chip

10

400

pF

7, 9

SDA and SCL Bus Pull-up Resistor

Off-chip

Maximum is determined by

For Cb = 400pF, max is about

2k

Ω.

For Cb = 40pF, max is about

15k

Ω

1k

Ω

7, 9

NOTES:

7. Parameter is not 100% tested.

10. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.

(Continued)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

(Note 10)

TYP

(Note 4)

MAX

(Note 10) UNITS

NOTES

ISL12032