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ISL6537A Datasheet(PDF) 10 Page - Intersil Corporation |
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ISL6537A Datasheet(HTML) 10 Page - Intersil Corporation |
10 / 16 page 10 FN9143.5 allows the termination voltage to float during the S3 sleep state. When the ISL6537A enables the VTT_DDR regulator or enters S0 state from a sleep state, this short is released and the internal divide down resistors which set the VTT_DDR voltage to 50% of VDDQ_DDR will provide a controlled voltage rise on the capacitor that is tied to the VREF_IN pin. The voltage on this capacitor is the reference for the VTT_DDR regulator and the output will track it as it settles to 50% of the VDDQ voltage. The combination of the internal resistors and the VREF_IN capacitor will determine the rise time of the VTT_DDR regulator (see the Functional Pin Description section for proper sizing of the VREF_IN capacitor). At time t6, a full soft-start cycle has passed from the time that the VTT_DDR regulator was enabled. At this time the VIDPGD comparator is enabled. Once enabled if the VTT_GMCH/CPU output is within regulation, the VIDPGD pin will be forced to a high impedance state. Active to Sleep (S0 to S3 Transition) When SLP_S3 goes LOW with SLP_S5 still HIGH, the ISL6537A will disable all the regulators except for the VDDQ regulator, which is continually supplied by the 5VDUAL rail. VIDPGD will also transition LOW. When VTT is disabled, the internal reference for the VTT regulator is internally shorted to the VTT rail. This allows the VTT rail to float. When floating, the voltage on the VTT rail will depend on the leakage characteristics of the memory and MCH I/O pins. It is important to note that the VTT rail may not bleed down to 0V. Figure 1 shows how the individual regulators are affected by the S3 state at time t7. Sleep to Active (S3 to S0 Transition) When SLP_S3 transitions from LOW to HIGH with SLP_S5 held HIGH and after the 12V rail exceeds POR, the ISL6537A will initiate the soft-start sequence. This sequence is very similar to the mechanical start soft-start sequencing. The transition from S3 to S0 is represented in Figure 1 between times t8 and t14. At time t8, the SLP_S3 signal transitions HIGH. This enables the ATX, which brings up the 12V rail. At time t9, the 12V rail has exceeded the POR threshold and the ISL6537A enters a reset mode that lasts for 3 soft-start cycles. At time t10, the 3 soft-start cycle reset is ended and the individual regulators are enabled and soft-started in the same sequence as the mechanical cold start sequence, with the exception that the VDDQ regulator is already enabled and in regulation. Active to Shutdown (S0 to S5 Transition) When the system transitions from active, S0, state to shutdown, S4/S5, state, the ISL6537A IC disables all regulators and forces the VIDPGD pin LOW. This transition is represented on Figure 1 at time t15. Fault Protection The ISL6537A monitors the VDDQ regulator for under and overvoltage events. The VDDQ regulator also has overcurrent protection. The internal VTT_DDR LDO regulator is monitored for under and overvoltage events. All other regulators, with the exception of the DAC LDO, are monitored for undervoltage events. An overvoltage event on either the VDDQ or VTT_DDR regulator will cause an immediate shutdown of all regulators. This can only be cleared by toggling the SLP_S5 signal such that the system enters the S5 sleep state and then transitions back to the active, S0, state. If a regulator experiences any other fault condition (an undervoltage or an overcurrent on VDDQ), then that regulator, and only that regulator, will be disabled and an internal fault counter will be incremented by 1. If the disabled regulator is used as the input for another regulator, then that cascoded regulator will also experience a fault condition due to a loss of input. The cascoded regulator will be disabled and the fault counter incremented by 1. At every fault occurrence, the internal fault counter is incremented by 1 and an internal Fault Reset Counter is cleared to zero. The Fault Reset Counter will increment once for every clock cycle (1 clock cycle is typically 1/250kHz, or 4 μs). If the Fault Reset Counter reaches a count of 16384 before another fault occurs, then the Fault Counter is cleared to 0. If a fault occurs prior to the Fault Reset Counter reaching a count of 16384, then the Fault Reset Counter is set back to zero. The ISL6537A will immediately shut down when the Fault Counter reaches a count of 4 when the system is restarting from an S5 state into the active, or S0, state. The ISL6537A will immediately shut down when the Fault Counter reaches a count of 5 at any other time. The 16384 counts that are required to reset the Fault Reset Counter represent 8 soft-start cycles, as one soft-start cycle is 2048 clock cycles. This allows the ISL6537A to attempt at least one full soft-start sequence to restart the faulted regulators. When attempting to restart a faulted regulator, the ISL6537A will follow the preset start up sequencing. If a regulator is already in regulation, then it will not be affected by the start up sequencing. VDDQ Overcurrent Protection The overcurrent function protects the switching converter from a shorted output by using the upper MOSFET on-resistance, rDS(ON), to monitor the current. This method enhances the converter’s efficiency and reduces cost by eliminating a current sensing resistor. The overcurrent function cycles the soft-start function in a hiccup mode to provide fault protection. A resistor (ROCSET) programs the overcurrent trip level (see Typical Application ISL6537A |
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