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ISL8485E Datasheet(PDF) 2 Page - Intersil Corporation |
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ISL8485E Datasheet(HTML) 2 Page - Intersil Corporation |
2 / 14 page 2 Pinout ISL8483E, ISL8485E (PDIP, SOIC) TOP VIEW RO RE DE DI 1 2 3 4 8 7 6 5 VCC B / Z A / Y GND D R Ordering Information PART NO. (BRAND) TEMP. RANGE (oC) PACKAGE PKG. DWG. # ISL8483EIB (8483EIB) -40 to 85 8 Ld SOIC M8.15 ISL8483EIB-T (8483EIB) -40 to 85 8 Ld SOIC Tape and Reel M8.15 ISL8483EIP -40 to 85 8 Ld PDIP E8.3 ISL8485ECB (8485ECB) 0 to 70 8 Ld SOIC M8.15 ISL8485ECB-T (8485ECB) 0 to 70 8 Ld SOIC Tape and Reel M8.15 ISL8485ECP 0 to 70 8 Ld PDIP E8.3 ISL8485EIB (8485EIB) -40 to 85 8 Ld SOIC M8.15 ISL8485EIB-T (8485EIB) -40 to 85 8 Ld SOIC Tape and Reel M8.15 ISL8485EIP -40 to 85 8 Ld PDIP E8.3 Truth Tables TRANSMITTING INPUTS OUTPUTS RE DE DI Z Y X 1101 X 1010 0 0 X High-Z High-Z 1 0 X High-Z * High-Z * *Shutdown Mode for ISL8483E (see Note 7) RECEIVING INPUTS OUTPUT RE DE A-B RO 00 ≥ +0.2V 1 00 ≤ -0.2V 0 0 0 Inputs Open 1 1 0 X High-Z* 1 1 X High-Z *Shutdown Mode for ISL8483E (see Note 7) Pin Descriptions PIN FUNCTION RO Receiver output: If A > B by at least 0.2V, RO is high; If A < B by 0.2V or more, RO is low; RO = High if A and B are unconnected (floating). RE Receiver output enable. RO is enabled when RE is low; RO is high impedance when RE is high. DE Driver output enable. The driver outputs, Y and Z, are enabled by bringing DE high. They are high impedance when DE is low. DI Driver input. A low on DI forces output Y low and output Z high. Similarly, a high on DI forces output Y high and output Z low. GND Ground connection. A/Y ±15kV HBM ESD Protected, RS-485/422 level noninverting receiver input and noninverting driver output. Pin is an input (A) if DE = 0; pin is an output (Y) if DE = 1. B/Z ±15kV HBM ESD Protected, RS-485/422 level inverting receiver input and inverting driver output. Pin is an input (B) if DE = 0; pin is an output (Z) if DE = 1. VCC System power supply input (4.5V to 5.5V). ISL8483E, ISL8485E |
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