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HIN241CB Datasheet(PDF) 11 Page - Intersil Corporation |
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HIN241CB Datasheet(HTML) 11 Page - Intersil Corporation |
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11 / 21 page  11 FN3138.16 September 26, 2008 Transmitters The transmitters are TTL/CMOS compatible inverters which translate the inputs to RS-232 outputs. The input logic threshold is about 26% of VCC, or 1.3V for VCC = 5V. A logic 1 at the input results in a voltage of between -5V and V- at the output, and a logic 0 results in a voltage between +5V and (V+ -0.6V). Each transmitter input has an internal 400k Ω pullup resistor so any unused input can be left unconnected and its output remains in its low state. The output voltage swing meets the RS-232C specifications of ±5V minimum with the worst case conditions of: all transmitters driving 3k Ω minimum load impedance, VCC = 4.5V, and maximum allowable operating temperature. The transmitters have an internally limited output slew rate which is less than 30V/µs. The outputs are short circuit protected and can be shorted to ground indefinitely. The powered down output impedance is a minimum of 300 Ω with ±2V applied to the outputs and VCC = 0V. Receivers The receiver inputs accept up to ±30V while presenting the required 3k Ω to 7kΩ input impedance even if the power is off (VCC = 0V). The receivers have a typical input threshold of 1.3V which is within the ±3V limits, known as the transition region, of the RS-232 specifications. The receiver output is 0V to VCC. The output will be low whenever the input is greater than 2.4V and high whenever the input is floating or driven between +0.8V and -30V. The receivers feature 0.5V hysteresis to improve noise rejection. The receiver Enable line EN, when set to logic “1”, (HIN236, HIN239, HIN240, and HIN241) disables the receiver outputs, placing them in the high impedance mode. The receiver outputs are also placed in the high impedance state when in shutdown mode. TOUT V- < VTOUT < V+ 300 Ω 400k Ω TXIN GND < TXIN < VCC V- V+ VCC FIGURE 2. TRANSMITTER ROUT GND < VROUT < VCC 5k Ω RXIN -30V < RXIN < +30V GND VCC FIGURE 3. RECEIVER TIN VOL VOL tPLH tPHL AVERAGE PROPAGATION DELAY = tPHL + tPLH 2 OR RIN TOUT OR ROUT FIGURE 4. PROPAGATION DELAY DEFINITION HIN232, HIN236, HIN237, HIN238, HIN239, HIN240, HIN241 |
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