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ISL98002CRZ-140 Datasheet(PDF) 11 Page - Intersil Corporation |
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ISL98002CRZ-140 Datasheet(HTML) 11 Page - Intersil Corporation |
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11 / 28 page  11 FN6535.0 March 26, 2008 0x05 Input configuration (0x00) 0 Reserved Set to 0. 1 Input Coupling 0: AC coupled (positive input connected to clamp DAC during clamp time, negative input disconnected from outside pad and always internally tied to appropriate clamp DAC) 1: DC coupled (+ and - inputs are brought to pads and never connected to clamp DACs). Analog clamp signal is turned off in this mode. 2 RGB/YPbPr 0: RGB inputs Base ABLC target code = 0x00 for R, G, and B) 1: YPbPr inputs Base ABLC target code = 0x00 for G (Y) Base ABLC target code = 0x80 for R (Pr) and B (Pb) 3 Sync Type 0: Separate HSYNC/VSYNC 1: Composite (from SOG or CSYNC on HSYNC) 4 Composite Sync Source 0: SOGIN 1: HSYNCIN Note: If Sync Type = 0, the multiplexer will pass HSYNCIN regardless of the state of this bit. 5 COAST CLAMP enable 0: DC restore clamping and ABLC™ suspended during COAST 1: DC restore clamping and ABLC™ continue during COAST 6 Sync Mask Disable 0: Interval between HSYNC pulses masked (preventing PLL from seeing Macrovision and any spurious glitches) 1: Interval between HSYNC pulses not masked (Macrovision will cause PLL to lose lock) 7 HSYNCOUT Mask Disable 0: HSYNCOUT signal is masked (any Macrovision, sync glitches on incoming SYNC are stripped from HSYNCOUT) 1: HSYNCOUT signal is not masked (any Macrovision, sync glitches on incoming SYNC appear on HSYNCOUT) If Sync Mask Disable = 1, HSYNCOUT is not masked. 0x06 Red Gain (0x55) 7:0 Red Gain Channel gain, where: gain (V/V) = 0.5 + [7:0]/170 0x00: gain = 0.5V/V (1.4VP-P input = full range of ADC) 0x55: gain = 1.0V/V (0.7VP-P input = full range of ADC) 0xFF: gain = 2.0V/V (0.35VP-P input = full range of ADC) 0x07 Green Gain (0x55) 7:0 Green Gain 0x08 Blue Gain (0x55) 7:0 Blue Gain Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) BIT(S) FUNCTION NAME DESCRIPTION ISL98002 |
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