7

FN6447.0

February 13, 2007

ISL8105B

pull down the voltage (at the RC rate of the R of the load and

the C of the output capacitance).

would go through its cycle, but with no output voltage ramp.

there may be excessive inrush current charging the output

capacitors (only the beginning of the ramp, from zero to

changing the sequencing of the power supplies, or sharing

the same supply, or adding sequencing logic to the

ready (see “Input Voltage Considerations” on page 9).

If the IC is disabled after soft-start (by pulling COMP/EN pin

low), and then enabled (by releasing the COMP/EN pin),

then the full initialization (including OCP sample) will take

place. However, there is no new OCP sampling during

overcurrent retries. If the output is shorted to GND during

soft-start, the OCP will handle it, as described in the next

section.

Overcurrent Protection (OCP)

The overcurrent function protects the converter from a

shorted output by using the bottom-side MOSFET's

Application Diagram). This method enhances the converter's

efficiency and reduces cost by eliminating a current sensing

resistor. If overcurrent is detected, the output immediately

shuts off, it cycles the soft-start function in a hiccup mode

(2 dummy soft-start time-outs, then up to one real one) to

provide fault protection. If the shorted condition is not

removed, this cycle will continue indefinitely.

Following POR (and 6.8ms delay), the ISL8105B initiates the

Overcurrent Protection sample and hold operation. The

BGATE driver is disabled to allow an internal 21.5µA current

samples this voltage (which is referenced to the GND pin) at

the BGATE/BSOC pin, and holds it in a counter and DAC

combination. This sampled voltage is held internally as the

Overcurrent Set Point, for as long as power is applied, or

until a new sample is taken after coming out of a shut-down.

The actual monitoring of the bottom-side MOSFET's

on-resistance starts 200ns (nominal) after the edge of the

internal PWM logic signal (that creates the rising external

BGATE signal). This is done to allow the gate transition

noise and ringing on the LX pin to settle out before

monitoring. The monitoring ends when the internal PWM

edge (and thus BGATE) goes low. The OCP can be detected

anywhere within the above window.

If the regulator is running at high TGATE duty cycles (around

87% for 300kHz operation), then the BGATE pulse width

may not be wide enough for the OCP to properly sample the

there at all) for 3 consecutive pulses, then the third pulse will

be stretched and/or inserted to the 425ns minimum width.

This allows for OCP monitoring every third pulse under this

condition. This can introduce a small pulse-width error on the

output voltage, which will be corrected on the next pulse;

and the output ripple voltage will have an unusual 3-clock

pattern, which may look like jitter. If the OCP is disabled (by

then the pulse stretching feature is also disabled. Figure 4

illustrates the BGATE pulse width stretching, as the width

gets smaller.

FIGURE 3. SOFT-START WITH PRE-BIAS

T0

T1

T2