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ISL6227CAZ Datasheet(PDF) 11 Page - Intersil Corporation |
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ISL6227CAZ Datasheet(HTML) 11 Page - Intersil Corporation |
11 / 27 page 11 FN9094.7 May 4, 2009 PG2/REF This pin has a double function, depending on the mode of operation. When the chip is used as a dual channel PWM controller (DDR = 0), the pin provides an open drain PGOOD2 function for the second channel the same way as PG1. The pin is pulled low when the second channel output is out of -11% to +15% of the set value. In DDR mode (DDR = 1), this pin is the output of the buffer amplifier that takes VDDQ/2 voltage applied to OCSET2 pin from the resister divider. It can source a typical 10mA current. OCSET2 In a dual channel application with DDR = 0, a resistor from this pin to ground sets the overcurrent threshold for the second channel controller. Its voltage is the buffered internal 0.9V reference. In the DDR application with DDR = 1, this pin connects to the center point of a resistor divider tracking the VDDQ/2. This voltage is then buffered by an amplifier voltage follower and sent to the PG2/REF pin. It sets the reference voltage of Channel 2 for its regulation. VCC This pin powers the controller. Typical Application Figures 31 and 32 show the application circuits of a dual channel DC/DC converter for a notebook PC. The power supply in Figure 31 provides +2.5V and +1.8V voltages for memory and the graphics interface chipset from a +5.0VDC to a 28VDC battery voltage. Figure 32 illustrates the application circuit for a DDR memory power solution. The power supply shown in Figure 32 generates +2.5V VDDQ voltage from a battery. The +1.25V VTT termination voltage tracks VDDQ/2 and is derived from +2.5V VDDQ. To complete the DDR memory power requirements, the +1.25V reference voltage is provided through the PG2 pin. ISL6227 |
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