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KAD5512P-17Q72 Datasheet(PDF) 6 Page - Intersil Corporation |
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KAD5512P-17Q72 Datasheet(HTML) 6 Page - Intersil Corporation |
6 / 36 page KAD5512P 6 FN6807.4 October 1, 2010 Pin Descriptions - 48 Ld QFN PIN NUMBER LVDS [LVCMOS] NAME LVDS [LVCMOS] FUNCTION 1, 9, 13, 17, 47 AVDD 1.8V Analog Supply 2-4, 11, 21, 22 DNC Do Not Connect 5, 8, 12, 48 AVSS Analog Ground 6, 7 VINN, VINP Analog Input Negative, Positive 10 VCM Common Mode Output 14, 15 CLKP, CLKN Clock Input True, Complement 16 NAPSLP Tri-Level Power Control (Nap, Sleep modes) 18 RESETN Power On Reset (Active Low, see page 19) 19, 29, 42 OVSS Output Ground 20, 37 OVDD 1.8V Output Supply 23 D0N [NC] LVDS DDR Logical Bits 1, 0 Output Complement [NC in LVCMOS] 24 D0P [D0] LVDS DDR Logical Bits 1, 0 Output True [CMOS DDR Logical Bits 1, 0 in LVCMOS] 25 D1N [NC] LVDS DDR Logical Bits 3, 2 Output Complement [NC in LVCMOS] 26 D1P [D1] LVDS DDR Logical Bits 3, 2 Output True [CMOS DDR Logical Bits 3, 2 in LVCMOS] 27 D2N [NC] LVDS DDR Logical Bits 5, 4 Output Complement [NC in LVCMOS] 28 D2P [D2] LVDS DDR Logical Bits 5, 4 Output True [CMOS DDR Logical Bits 5, 4 in LVCMOS] 30 RLVDS LVDS Bias Resistor (Connect to OVSS with a 10kΩ, 1% resistor) 31 CLKOUTN [NC] LVDS Clock Output Complement [NC in LVCMOS] 32 CLKOUTP [CLKOUT] LVDS Clock Output True [LVCMOS CLKOUT] 33 D3N [NC] LVDS DDR Logical Bits 7, 6 Output Complement [NC in LVCMOS] 34 D3P [D3] LVDS DDR Logical Bits 7, 6 Output True [CMOS DDR Logical Bits 7, 6 in LVCMOS] 35 D4N [NC] LVDS DDR Logical Bits 9, 8 Output Complement [NC in LVCMOS] 36 D4P [D4] LVDS DDR Logical Bits 9, 8 Output True [CMOS DDR Logical Bits 9, 8 in LVCMOS] 38 D5N [NC] LVDS DDR Logical Bits 11, 10 Output Complement [NC in LVCMOS] 39 D5P [D5] LVDS DDR Logical Bits 11, 10 Output True [CMOS DDR Logical Bits 11, 10 in LVCMOS] 40 ORN [NC] LVDS Over Range Complement [NC in LVCMOS] 41 ORP [OR] LVDS Over Range True [LVCMOS Over Range] 43 SDO SPI Serial Data Output (4.7kΩ pull-up to OVDD is required) 44 CSB SPI Chip Select (active low) 45 SCLK SPI Clock 46 SDIO SPI Serial Data Input/Output PAD (Exposed Paddle) AVSS Analog Ground (Connect to a low thermal impedance analog ground plane with multiple vias) NOTE: LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection). |
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