10

4545D–BCD–04/09

U6815BM

Serial Interface - Logic Inputs (DI, CLK, CS)

Input voltage low level threshold

Pins 24 to 26

V

IL

0.3

×

V

VCC

V

Input voltage high level threshold

Pins 24 to 26

0.7

×

V

VCC

V

Hysteresis of input voltage

Pins 24 to 26

ΔV

I

50

500

mV

Pull-down current, Pins DI and CLK

V

I

PDSI

250

µA

Pull-up current Pin CS

V

I

PUSI

–50

–2

µA

Serial Interface - Logic Output (DO)

Output voltage low level

I

V

DOL

0.5

V

Output voltage high level

I

V

DOH

V

1V

V

Leakage current (tristate)

–10

10

mA

12. Electrical Characteristics (Continued)

Parameters

Test Conditions/Pins

Symbol

Min.

Typ.

Max.

Unit

Notes:

1. Only valid for version U6815BM-N.

2. Delay time between rising edge of CS after data transmission and switch-on output stages to 90% of final level.

13. Serial Interface – Timing

Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

DO enable after CS

falling edge

C

1

t

ENDO

200

ns

DO disable after CS

rising edge

2

200

ns

DO fall time

C

–

t

DOf

100

ns

DO rise time

C

–

t

DOr

100

ns

DO valid time

C

10

t

DOVal

200

ns

CS setup time

4

t

CSSethl

225

ns

CS setup time

V

8t

CSSetlh

225

ns

CS high time

Input register,

Bit 14 (SCT) = high

140

ns

Input register,

Bit 14 (SCT) = low

9t

CSh

17.5

ns

CLK high time

5

225

ns

CLK low time

6

225

ns

CLK period time

–

500

ns

CLK setup time

7

225

ns

CLK setup time

3

225

ns

DI setup time

11

t

DIset

40

ns

DI hold time

12

t

DIHold

40

ns

Note:

1. see Figure 13-1 on page 11