W78L801

- 8 -

is set to 1. i.e. User’s applications should elude the ALE pulses before software configure it with I/O

port P4.5.

Bit:

7

6

5

4

3

2

1

0

-

P4.6

P4.5

-

P4.3

P4.2

P4.1

P4.0

Mnemonic: P4

Address: D8H

6.1 Interrupt System

vectors to a specific location in program memory for its interrupt service routine. Each of these

sources can be individually enabled or disabled by setting or clearing the corresponding bit in Special

Function Register IE0 and IE1. The individual interrupt priority level depends on the Interrupt Priority

Register IP0 and IP1. Additional external interrupts INT2 to INT9 are level sensitive and may be used

to awake the device from power down mode. The Port 1 interrupts can be initialized to either active

HIGH or LOW via setting the Interrupt Polarity Register IX. The IRQ register contains the flags of Port

1 interrupts. Each flag in IRQ register will be set when an interrupt request is recognized but must be

cleared by software

. Note that the interrupt flags have to be cleared before the interrupt service

routine is completed, or else another interrupt will be generated.

Interrupt Enable Register 0

Bit:

7

6

5

4

3

2

1

0

EA

-

-

-

ET1

EX1

ET0

EX0

Mnemonic: IE

Address: A8H

EA : Global enable. Enable/disable all interrupts.

ET1: Enable Timer 1 interrupt

EX1: Enable external interrupt 1

ET0: Enable Timer 0 interrupt

EX0: Enable external interrupt 0

Interrupt Enable Register 1

Bit:

7

6

5

4

3

2

1

0

EX9

EX8

EX7

EX6

EX5

EX4

EX3

EX2

Mnemonic: IE1

Address: E8H

EX9: Enable external interrupt 9

EX8: Enable external interrupt 8

EX7: Enable external interrupt 7

EX6: Enable external interrupt 6

EX5: Enable external interrupt 5

EX4: Enable external interrupt 4

EX3: Enable external interrupt 3

EX2: Enable external interrupt 2