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SST25VF064C-80-4C-S3AE Datasheet(PDF) 9 Page - Silicon Storage Technology, Inc |
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SST25VF064C-80-4C-S3AE Datasheet(HTML) 9 Page - Silicon Storage Technology, Inc |
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9 / 31 page  Data Sheet 64 Mbit SPI Serial Dual I/O Flash SST25VF064C 9 ©2010 Silicon Storage Technology, Inc. S71392-04-000 04/10 INSTRUCTIONS Instructions are used to read, write (Erase and Program), and configure the SST25VF064C. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. The Write-Enable (WREN) instruction must be executed prior any Page-Program, Dual-Input Page-Pro- gram, Sector-Erase, Block-Erase, Write-Status-Register, Chip-Erase, Program SID, or Lockout SID instructions. The complete list of instructions is provided in Table 6. All instructions are synchronized off a high to low transition of CE#. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. CE# must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for Read, Read-ID, and Read-Status-Register instructions). Any low to high transition on CE#, before receiving the last bit of an instruction bus cycle, will termi- nate the instruction in progress and return the device to standby mode. Instruction commands (Op Code), addresses, and data are all input from the most significant bit (MSB) first. TABLE 6: Device Operation Instructions Instruction Description Op Code Cycle1 1. One bus cycle is eight clock periods. Address Cycle(s)2 2. Address bits above the most significant bit can be either VIL or VIH. Dummy Cycle(s) Data Cycle(s) Read Read Memory 0000 0011b (03H) 3 0 1 to ∞ Fast-Read Dual I/O Read Memory with Dual Address Input and Data Output 1011 1011b (BBH) 33 3. One bus cycle is four clock periods (dual operation) 13 1 to ∞3 Fast-Read Dual-Output Read Memory with Dual Output 0011 1011b (3BH) 3 1 1 to ∞3 High-Speed Read Read Memory at Higher Speed 0000 1011b (0BH) 3 1 1 to ∞ Sector-Erase4 4. 4KByte Sector Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either at VIL or VIH. Erase 4 KByte of memory array 0010 0000b (20H) 3 0 0 32 KByte Block-Erase5 Erase 32KByte block of memory array 0101 0010b (52H) 3 0 0 64 KByte Block-Erase6 Erase 64 KByte block of memory array 1101 1000b (D8H) 3 0 0 Chip-Erase Erase Full Memory Array 0110 0000b (60H) or 1100 0111b (C7H) 000 Page-Program To Program 1 to 256 Data Bytes 0000 0010b (02H) 3 0 1 to 256 Dual-Input Page- Program To Program 1 to 256 Data Bytes 1010 0010b (A2H) 3 0 1 to 1283 RDSR7 Read-Status-Register 0000 0101b (05H) 0 0 1 to ∞ EWSR Enable-Write-Status-Register 0101 0000b (50H) 0 0 0 WRSR Write-Status-Register 0000 0001b (01H) 0 0 1 WREN Write-Enable 0000 0110b (06H) 0 0 0 WRDI Write-Disable 0000 0100b (04H) 0 0 0 RDID8 Read-ID 1001 0000b (90H) or 1010 1011b (ABH) 30 1 to ∞ JEDEC-ID JEDEC ID Read 1001 1111b (9FH) 0 0 3 to ∞ EHLD Enable HOLD# pin functionality of the RST#/ HOLD# pin 1010 1010b (AAH) 0 0 0 Read SID Read Security ID 1000 1000b (88H) 1 1 1 to 32 Program SID9 Program User Security ID area 1010 0101b (A5H) 1 0 1 to 24 Lockout SID9 Lockout Security ID Programming 1000 0101b (85H) 0 0 0 T6.0 1392 |
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