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REJ03B0267-0101 Rev.1.01 Page 82 of 156 Jul 23, 2010 M16C/5M Group, M16C/57 Group 5. Electrical Characteristics J-Version 5.1.2 Recommended Operating Conditions Notes: 1. The mean output current is the mean value within 100ms. 2. Refer to Figure 5.1 “Main clock input oscillation frequency, PLL clock oscillation frequency” for the relationship between main clock oscillation frequency/PLL clock oscillation frequency and supply voltage. Table 5.2 Operating Conditions (1) VCC = 3.0 V to 5.5 V, Topr = -40°C to 85°C unless otherwise specified. Symbol Characteristic Value Unit Min. Typ. Max. VCC Supply voltage 3.0 5.5 V AVCC Analog supply voltage VCC V VSS Ground voltage 0V AVSS Analog ground voltage 0V VIH High level input voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 Input level 0.50 VCC 0.7 VCC VCC V Input level 0.70 VCC 0.85VCC VCC V XIN, RESET, CNVSS 0.8 VCC VCC SDAMM, SCLMM When I2C-bus input level selected 0.7 VCC VCC V When SMBUS input level selected 2.1 VCC V VIL Low level input voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 Input level 0.50 VCC 0 0.3 VCC V Input level 0.70 VCC 0 0.45VCC V XIN, RESET, CNVSS 0 0.2 VCC V SDAMM, SCLMM When I2C-bus input level selected 0 0.3 VCC V When SMBUS input level selected 0 0.8 V IOH(sum) High peak output current Sum of IOH(peak) at P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7 -80.0 mA IOH(peak) High level peak output current P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7 -10.0 mA IOH(avg) High level average output current (1) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7 -5.0 mA IOL(sum) Low peak output current Sum of IOL(peak) at P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 80.0 mA IOL(peak) Low level peak output current P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 10.0 mA IOL(avg) Low level average output current (1) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 5.0 mA f(XIN) Main clock input oscillation frequency (2) 020 MHz f(XCIN) Sub clock oscillation oscillator frequency 32.768 50 kHz f(PLL) PLL clock oscillation frequency (2) 10 32 MHz f(BCLK) CPU operation frequency 0 32 MHz tsu(PLL) Wait time to stabilize PLL frequency synthesizer 1 ms |
