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SST49LF004B Datasheet(PDF) 1 Page - Silicon Storage Technology, Inc

Part # SST49LF004B
Description  4 Mbit Firmware Hub
Download  36 Pages
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Manufacturer  SST [Silicon Storage Technology, Inc]
Direct Link  http://www.sst.com/
Logo SST - Silicon Storage Technology, Inc

SST49LF004B Datasheet(HTML) 1 Page - Silicon Storage Technology, Inc

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©2007 Silicon Storage Technology, Inc.
S71307-03-EOL
12/07
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
Intel is a registered trademark of Intel Corporation.
These specifications are subject to change without notice.
EOL Data Sheet
FEATURES:
4 Mbit SuperFlash memory array for code/data
storage
– SST49LF004B: 512K x8 (4 Mbit)
Conforms to Intel LPC Interface Specification
– Supports Single-Byte Firmware Memory
Cycle Type
Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 64 KByte overlay blocks
– Chip-Erase for PP Mode Only
Single 3.0-3.6V Read and Write Operations
Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
Low Power Consumption
– Active Read Current: 6 mA (typical)
– Standby Current: 10 µA (typical)
Fast Sector-Erase/Byte-Program Operation
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time: 8 seconds (typical)
– Single-pulse Program or Erase
– Internal timing generation
CMOS and PCI I/O Compatibility
Two Operational Modes
– Low Pin Count (LPC) interface mode for
in-system operation
– Parallel Programming (PP) mode for fast
production programming
•Low Pin Count (LPC) Interface Mode
– LPC bus interface supporting byte Read and
Write
– 33 MHz clock frequency operation
– WP# and TBL# pins provide hardware write
protect for entire chip and/or top Boot Block
– Block Locking Registers for individual block
Write-Lock and Lock-Down protection
– JEDEC Standard SDP Command Set
– Data# Polling and Toggle Bit for End-of-Write
detection
– 5 GPI pins for system design flexibility
– 4 ID pins for multi-chip selection
Parallel Programming (PP) Mode
– 11-pin multiplexed address and 8-pin data
I/O interface
– Supports fast In-System or PROM programming
for manufacturing
Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST49LF004B flash memory devices are designed to
interface with host controllers (chipsets) that support a low-
pin-count (LPC) interface for BIOS applications. The
SST49LF004B devices comply with Intel’s LPC Interface
Specification, supporting single-byte Firmware Memory
cycle type.
The SST49LF004B devices are backward compatible to
the SST49LF004A Firmware Hub. In this document, FWH
mode in the SST49LF004A specification is referenced as
the Firmware Memory Read/Write cycle. Two interface
modes are supported by the SST49LF004B: LPC mode
(Firmware Memory cycle types) for in-system operations
and Parallel Programming (PP) mode to interface with pro-
gramming equipment.
The SST49LF004B flash memory devices are manufac-
tured with SST’s proprietary, high-performance SuperFlash
technology. The split-gate cell design and thick-oxide tun-
neling injector attain greater reliability and manufacturability
compared
with
alternative
approaches.
The
SST49LF004B devices significantly improve performance
and reliability, while lowering power consumption. The
SST49LF004B devices write (Program or Erase) with a
single 3.0-3.6V power supply.
The SST49LF004B use less energy during Erase and Pro-
gram than alternative flash memory technologies. The total
energy consumed is a function of the applied voltage, cur-
rent and time of application. Since for any given voltage
range the SuperFlash technology uses less current to pro-
gram and has a shorter erase time, the total energy con-
sumed during any Erase or Program operation is less than
alternative flash memory technologies.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. This means the system software
or hardware does not have to be calibrated or correlated to
the cumulative number of Erase cycles as is necessary
with alternative flash memory technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
4 Mbit Firmware Hub
SST49LF004B
SST49LF002B / 003B / 004B4Mb Firmware Hub


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