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SST25WF010-40-5I-QAF Datasheet(PDF) 10 Page - Silicon Storage Technology, Inc |
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SST25WF010-40-5I-QAF Datasheet(HTML) 10 Page - Silicon Storage Technology, Inc |
10 / 32 page 10 Data Sheet 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 ©2009 Silicon Storage Technology, Inc. S71328-08-000 11/09 INSTRUCTIONS Instructions are used to read, write (Erase and Program), and configure the SST25WF512/010/020/040. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. The Write-Enable (WREN) instruction must be executed prior to Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, Write-Status-Register, or Chip-Erase instruc- tions. The complete instructions are provided in Tables 9 and 10. All instructions are synchronized off a high-to-low transition of CE#. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. CE# must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for Read, Read-ID, and Read-Status- Register instructions). Any low-to-high transition on CE#, before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to standby mode. Instruction commands (Op Code), addresses, and data are all input from the most significant bit (MSB) first. TABLE 9: Device Operation Instructions for SST25WF512 and SST25WF010 Instruction Description Op Code Cycle1 1. One bus cycle is eight clock periods. Address Cycle(s)2 2. Address bits above the most significant bit of each density can be VIL or VIH. Dummy Cycle(s) Data Cycle(s) Maximum Frequency Read Read Memory 0000 0011b (03H) 3 0 1 to ∞ 20 MHz High-Speed Read Read Memory at Higher Speed 0000 1011b (0BH) 3 1 1 to ∞ 40 MHz 4 KByte Sector- Erase3 3. 4 KByte Sector-Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either at VIL or VIH. Erase 4 KByte of memory array 0010 0000b (20H) 3 0 0 32 KByte Block- Erase4 4. 32 KByte Block-Erase addresses: use AMS-A15, remaining addresses are don’t care but must be set either at VIL or VIH. Erase 32 KByte block of memory array 0101 0010b (52H) 3 0 0 Chip-Erase Erase Full Memory Array 0110 0000b (60H) or 1100 0111b (C7H) 00 0 Byte-Program To Program One Data Byte 0000 0010b (02H) 3 0 1 AAI-Word-Program5 5. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of data to be programmed. Data Byte 0 will be programmed into the initial address [A23-A1] with A0=0, Data Byte 1 will be programmed into the initial address [A23-A1] with A0 = 1. Auto Address Increment Programming 1010 1101b (ADH) 3 0 2 to ∞ RDSR6 6. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#. Read-Status-Register 0000 0101b (05H) 0 0 1 to ∞ EWSR7 7. Either EWSR or WREN followed by WRSR will write to the Status register. The EWSR-WRSR sequence provides backward compat- ibility to the SST25VF/LF series. The WREN-WRSR sequence is recommended for new designs. Enable-Write-Status-Register 0110 0000b (50H) 0 0 0 WRSR Write-Status-Register 0000 0001b (01H) 0 0 1 WREN7 Write-Enable 0000 0110b (06H) 0 0 0 WRDI Write-Disable 0000 0100b (04H) 0 0 0 RDID8 8. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer’s ID and device ID output stream is continuous until terminated by a low-to-high transition on CE#. Read-ID 1001 0000b (90H) or 1010 1011b (ABH) 30 1 to ∞ EBSY Enable SO to output RY/BY# status during AAI programming 0111 0000b (70H) 0 0 0 DBSY Disable SO to output RY/BY# status during AAI programming 1000 0000b (80H) 0 0 0 JEDEC-ID JEDEC ID read 1001 1111b (9FH) 0 0 3 to ∞ EHLD Enable HOLD# pin functionality of the RST#/HOLD# pin 1010 1010b (AAH) 0 0 0 T9.0 1328 |
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