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SST25VF040B-80-4I-S2AF Datasheet(PDF) 10 Page - Silicon Storage Technology, Inc |
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SST25VF040B-80-4I-S2AF Datasheet(HTML) 10 Page - Silicon Storage Technology, Inc |
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10 / 33 page  10 Data Sheet 4 Mbit SPI Serial Flash SST25VF040B ©2009 Silicon Storage Technology, Inc. S71295-05-000 10/09 High-Speed-Read (50/80 MHz) The High-Speed-Read instruction supporting up to 50 MHz (for SST25VF040B-50-xx-xxF) or 80 MHz (for SST25VF040B-80-xx-xxE) Read is initiated by executing an 8-bit command, 0BH, followed by address bits [A23-A0] and a dummy byte. CE# must remain active low for the duration of the High-Speed-Read cycle. See Figure 6 for the High-Speed-Read sequence. Following a dummy cycle, the High-Speed-Read instruc- tion outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE#. The internal address pointer will automatically incre- ment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap- around) of the address space. Once the data from address location 7FFFFH has been read, the next output will be from address location 00000H. FIGURE 6: High-Speed-Read Sequence 1295 HSRdSeq.0 CE# SO SI SCK ADD. 012 3 4 5 6 7 8 ADD. ADD. 0B HIGH IMPEDANCE 15 16 23 24 31 32 39 40 47 48 55 56 63 64 N+2 N+3 N+4 N N+1 X MSB MSB MSB MODE 0 MODE 3 DOUT DOUT DOUT DOUT 80 71 72 DOUT Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (VIL or VIH) |
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