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SST25VF064C Datasheet(PDF) 11 Page - Silicon Storage Technology, Inc |
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SST25VF064C Datasheet(HTML) 11 Page - Silicon Storage Technology, Inc |
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11 / 31 page  Data Sheet 64 Mbit SPI Serial Dual I/O Flash SST25VF064C 11 ©2010 Silicon Storage Technology, Inc. S71392-04-000 04/10 FIGURE 7: High-Speed Read Sequence Fast-Read Dual-Output (75 MHz) The Fast-Read Dual-Output (3BH) instruction outputs data up to 75 MHz from the SIO0 and SIO1 pins. To initiate the instruction, execute an 8-bit command (3BH) followed by address bits A23-A0 and a dummy byte on SI/SIO0. Fol- lowing a dummy cycle, the Fast-Read Dual-Output instruc- tion outputs the data starting from the specified address location on the SIO1 and SIO0 lines. SIO1 outputs, per clock sequence, odd data bits D7, D5, D3, and D1; and SIO0 outputs even data bits D6, D4, D2, and D0. CE# must remain active low for the duration of the Fast-Read Dual- Output instruction cycle. See Figure 8 for the Fast-Read Dual-Output sequence. The data output stream is continuous through all addresses until terminated by a low-to-high transition on CE#. The internal address pointer will automatically incre- ment until the highest memory address is reached. Once the highest memory address is reached, the address pointer automatically increments to the beginning (wrap- around) of the address space. for 64 Mbit density, once the data from address location 7FFFFFH has been read the next output will be from address location 000000H. FIGURE 8: Fast-Read Dual Output Sequence 1392 F07.0 CE# SO SI SCK ADD. 012 34 5 6 7 8 ADD. ADD. 0B HIGH IMPEDANCE 15 16 23 24 31 32 39 40 47 48 55 56 63 64 N+2 N+3 N+4 N N+1 X MSB MODE 0 MODE 3 DOUT DOUT DOUT DOUT 80 71 72 DOUT 1392 F08.1 CE# SIO1 SIO0 SCK 012 3 4 5 6 7 8 28 29 30 31 MSB MODE 3 MODE 0 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 6 4 20 6 4 20 6 4 20 6 4 20 75 3 1 75 3 1 75 3 1 75 3 1 24-Bit Address Dummy Cycle DOUT MSB DOUT MSB DOUT MSB DOUT 3B N N+1 N+2 N+3 IO, Switches from Input to Output X ADD. ADD. ADD. 15 16 HIGH IMPEDANCE |
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