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REJ03B0297-0100 Rev.1.00 Page 21 of 99 Jul 16, 2010 R32C/116A Group 1. Overview Table 1.16 Pin Definitions and Functions (2/4) Bus control pins BC0/D0, BC2/D1 I/O Output of byte control ( BC0 and BC2) and input/output of data (D0 and D1) by time-division while accessing an external memory space with multiplexed bus CS0 to CS3 O Chip select output WR0/WR1/WR2/ WR3, WR/BC0/BC1/ BC2/BC3, RD O Output of write, byte control, and read signals. Either WRx or WR and BCx can be selected by a program. Data is read when RD is low. • When WR0, WR1, WR2, WR3, and RD are selected, data is written to the following address: 4n+0, when WR0 is low 4n+1, when WR1 is low 4n+2, when WR2 is low 4n+3, when WR3 is low on 32-bit external data bus or an even address, when WR0 is low an odd address, when WR1 is low on 16-bit external data bus • When WR, BC0, BC1, BC2, BC3, and RD are selected, data is written, when WR is low and the following address is accessed: 4n+0, when BC0 is low 4n+1, when BC1 is low 4n+2, when BC2 is low 4n+3, when BC3 is low on 32-bit external data bus or an even address, when BC0 is low an odd address, when BC1 is low on 16-bit external data bus ALE O Latch enable signal in multiplexed bus format HOLD I The MCU is in a hold state while this pin is held low HLDA O This pin is driven low while the MCU is held in a hold state RDY I Bus cycle is extended by the CPU if this pin is low on the falling edge of the BCLK |
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