5

0778L–PLD–8/10

Atmel ATF22V10C(Q)Z

4.4

Input Test Waveforms

4.4.1

Input Test Waveforms and Measurement Levels

4.4.2

Output Test Loads

Note:

Similar competitors devices are specified with slightly different loads. These load differences may affect output signals’

delay and slew rate. Atmel devices are tested with sufficient margins to meet compatible device specification

conditions.

4.5

Pin Capacitance

Table 4-1.

Pin Capacitance (f = 1MHz,T=25C(1)

Note:

1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested

4.6

Power-up Reset

from V

buffer.

This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the

uncertainty of how V

1.

The V

2.

The clock must remain stable during T

PR

3.

After T

4.7

Preload of Register Outputs

The ATF22V10CZ/CQZ’s registers are provided with circuitry to allow loading of each register with either a high or

a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A

JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC

file preload sequence will be done automatically by most of the approved programmers after the programming.

Typ

Max

Units

Conditions

C

IN

810

pF

V

C

I/O

810

pF

V