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24-Bit, Single-Channel, Ultra-Low-Power,

Delta-Sigma ADCs with GPIO

Detailed Description

The MAX11200/MAX11210 are ultra-low-power (< 300FA

active), high-resolution, low-speed, serial-output ADCs.

These ADCs provide the highest resolution per unit

power in the industry, and are optimized for applications

that require very high dynamic range with low power

such as sensors on a 4mA to 20mA industrial control

loop. Optional input buffers provide isolation of the signal

inputs from the switched capacitor sampling network,

allowing the devices to be used with very high imped-

ance sources without compromising available dynamic

range. The devices provide a high-accuracy internal

oscillator, which requires no external components. When

used with the specified data rates, the internal digital fil-

ter provides more than 144dB rejection of 50Hz or 60Hz

line noise. The devices are highly configurable using the

SPI interface and include four GPIOs for external mux

control.

Analog Inputs

The devices accept two analog inputs (AINP, AINN) in

buffered or unbuffered mode. The input buffer isolates

the inputs from the capacitive load presented by the

modulator, allowing for high source-impedance analog

transducers. The value of the SIGBUF bit in the CTRL1

register determines whether the input buffer is enabled

or disabled. See Table 12.

Input Voltage Range

The modulator input range is programmable for bipolar

bit in the CTRL1 register configures the devices for uni-

polar or bipolar transfer functions. See Table 12.

System Clock

The devices incorporate a highly stable internal oscillator

that provides the system clock. The system clock runs

the internal state machine and is trimmed to 2.4576MHz

or 2.048MHz. The internal oscillator clock is divided

down to run the digital and analog timing. The LINEF bit

in the CTRL1 register determines the internal oscillator

frequency. See Tables 10 and 12. Set LINEF = 0 to select

the 2.4576MHz oscillator and LINEF = 1 to select the

2.048MHz oscillator. The 2.4576MHz oscillator provides

maximum 60Hz rejection, and the 2.048MHz oscillator

Table 1. Continuous Conversion with SCYCLE Bit = 0

Table 2. Single-Cycle Conversion with SCYCLE Bit = 1

*LINEF bit = 0 sets the clock frequency to 2.4576MHz and the input sampling frequency to 245.76kHz. LINEF bit = 1 sets the

clock frequency to 2.048MHz and the input sampling frequency to 204.8kHz.

*LINEF bit = 0 sets the clock frequency to 2.4576MHz and the input sampling frequency to 245.76kHz. LINEF bit = 1 sets the

clock frequency to 2.048MHz and the input sampling frequency to 204.8kHz.

RATE[2:0]

DATA RATE* (sps)

BIPOLAR NFR

(BITS)

BIPOLAR

ENOB (BITS)

UNIPOLAR

NFR (BITS)

UNIPOLAR

ENOB (BITS)

OUTPUT NOISE

LINEF = 0

LINEF = 1

100

60

50

20.5

23.2

19.5

22.2

0.74

101

120

100

20.0

22.7

19.0

21.7

1.03

110

240

200

19.5

22.2

18.5

21.2

1.45

111

480

400

19.0

21.7

18.0

20.7

2.21

RATE[2:0]

SINGLE-CYCLE DATA RATE*

(sps)

BIPOLAR

NFR (BITS)

BIPOLAR

ENOB (BITS)

UNIPOLAR

NFR (BITS)

UNIPOLAR

ENOB (BITS)

OUTPUT NOISE

LINEF = 0

LINEF = 1

000

1

0.833

22.3

24.0

21.3

24.0

0.21

001

2.5

2.08

22

24.0

21.0

23.7

0.27

010

5

4.17

21.4

24.0

20.4

23.1

0.39

011

10

8.33

20.9

23.6

19.9

22.6

0.57

100

15

12.5

20.5

23.2

19.5

22.2

0.74

101

30

25

20.0

22.7

19.0

21.7

1.03

110

60

50

19.5

22.2

18.5

21.2

1.45

111

120

100

19.0

21.7

18.0

20.7

2.21