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NCT1008CMT3R2G Datasheet(PDF) 3 Page - ON Semiconductor |
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NCT1008CMT3R2G Datasheet(HTML) 3 Page - ON Semiconductor |
3 / 20 page NCT1008 http://onsemi.com 3 PIN ASSIGNMENT Pin No. Mnemonic Description 1 VDD Positive Supply, 2.8 V to 3.6 V. 2 D+ Positive Connection to Remote Temperature Sensor. 3 D− Negative Connection to Remote Temperature Sensor. 4 THERM Open−Drain Output. Can be used to turn a fan on/off or throttle a CPU clock in the event of an overtemperature condition. Requires pullup resistor. 5 GND Supply Ground Connection. 6 ALERT/THERM2 Open−Drain Logic Output Used as Interrupt or SMBus ALERT. This can also be configured as a second THERM output. Requires pullup resistor to VDD. 7 SDATA Logic Input/Output, SMBus Serial Data. Open−Drain Output. Requires pullup resistor. 8 SCLK Logic Input, SMBus Serial Clock. Requires pullup resistor. NOTE: The ground slug on 3x3 package can be left unconnected. SMBus/I2C TIMING SPECIFICATIONS (Note 1) Parameter Limit at TMIN and TMAX Unit Description fSCLK 400 kHz max − tLOW 1.3 ms min Clock low period, between 10% points. tHIGH 0.6 ms min Clock high period, between 90% points. tR 300 ns max Clock/data rise time. tF 300 ns max Clock/data fall time. tSU; STA 600 ns min Start condition setup time. tHD; STA (Note 2) 600 ns min Start condition hold time. tSU; DAT (Note 3) 100 ns min Data setup time. tSU; STO (Note 4) 600 ns min Stop condition setup time. tBUF 1.3 ms min Bus free time between stop and start conditions. 1. Guaranteed by design, but not production tested. 2. Time from 10% of SDATA to 90% of SCLK. 3. Time for 10% or 90% of SDATA to 10% of SCLK. 4. Time for 90% of SCLK to 10% of SDATA. Figure 2. Serial Bus Timing SCLK SDATA tR tF tLOW tHD;DAT tHD;STA tHIGH tSU;DAT STOP START STOP START tSU;STA tSU;STO tHD;STA tBUF |
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