D2-45057, D2-45157

10

FN6785.0

July 29, 2010

Pin Description

PIN

PIN

NAME

(Note 13) TYPE

VOLTAGE

LEVEL

(V)

DESCRIPTION

1

nRESET

I

3.3

Active low reset input with hysteresis. Low level activates system level reset, initializing all

internal logic and program operations. System latches boot mode selection on the IRQ input

pins on the rising edge.

2TEMPCOM/

TIO0

I/O

3.3

Board temperature monitor common I/O pin. When operating as output, provides 16mA

drive strength.

3

SDA

I/O

3.3

Two-Wire Serial data port, open drain driver with 8mA drive strength. Bidirectional signal

used by both the master and slave controllers for data transport. Pin floats on reset.

4

SCL

I/O

3.3

Two-Wire Serial clock port, open drain driver with 8mA drive strength. Bidirectional signal

is used by both the master and slave controllers for clock signaling. Pin floats on reset.

5SCLK

I

3.3

6SDIN

I

3.3

7LRCK

I

3.3

8MCLK

O

3.3

Output is an 8mA driver.

9

CVDD

P

3.3

Core power, +1.8VDC. Used in the chip internal DSP, logic and interfaces.

10

CGND

GND

3.3

Core ground.

11

RGND

GND

3.3

Digital pad ring ground. Internally connected to PWMGND.

12

RVDD

P

3.3

Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and

receivers, except for the analog pads. There are 2 of these pins and both are required to be

connected. Internally connected to PWMVDD.

13 TEMPREF/

SCK

I/O

3.3

Reference pin for temperature monitor and SPI clock. At de-assertion of device reset, pin

operates as SPI clock with 8mA drive strength. Upon internal D2-45057, D2-45157 firmware

execution, pin becomes temperature monitor reference.

14

nMUTE/

TIO1

O

3.3

Mute signal output. Low active: mute condition drives pin low. Output is a 16mA driver.

Initializes as input on reset, then becomes output upon internal firmware execution.

15

VOL1/

MISO

I/O

3.3

Volume control pulse input and SPI master- input/slave-output data signal. At de-assertion

of device reset, pin operates as SPI master input or slave output. (When operating as

output, provides 4mA drive strength.) Then upon internal D2-45057, D2-45157 firmware

execution, pin becomes input for monitoring up/down phase pulses from volume control.

(1 of 2 volume input pins.)

16

TEMP1/

MOSI

I/O

3.3

Board temperature monitor pin, and SPI master-output/slave-input data signal. At de-

assertion of device reset, pin operates as SPI master output or slave input. (When operating

as output, provides 4mA drive strength.) Then upon internal D2-45057, D2-45157 firmware

execution, pin becomes input for monitoring board temperature.

17

SPDIFRX

I

3.3

S/PDIF Digital audio data input

18

SPDIFTX

O

3.3

S/PDIF Digital audio data output This pin is the S/PDIF audio output and drives a 8mA, 3.3V

stereo output up to 192kHz. Pin floats on reset.

19

TEST

I

3.3

Hardware test mode control. For factory use only. Must be tied low.

20

IRQA

I

3.3

Interrupt request port A. One of 2 IRQ pins, tied to logic (3.3V) high or to ground. High/low

logic status establishes boot mode selection upon de-assertion of reset (nRESET) cycle.

21

IRQB

I

3.3

Interrupt request port B. One of 2 IRQ pins, tied to logic (3.3V) high or to ground. High/low

logic status establishes boot mode selection upon de-assertion of reset (nRESET) cycle.

22

RGND

GND

3.3

Digital pad ring ground. Internally connected to PWMGND.

23

RVDD

P

3.3

Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and

receivers, except for the analog pads. There are 2 of these pins and both are required to be

connected. Internally connected to PWMVDD.