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K7P401822M-H19 Datasheet(PDF) 2 Page - Samsung semiconductor |
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2 / 12 page Rev 1.0 K7P401822M 128Kx36 & 256Kx18 SRAM - 2 - K7P403622M Dec. 1998 PIN DESCRIPTION Pin Name Pin Description Pin Name Pin Description K, K Differential Clocks VDDQ Output Power Supply SAn Synchronous Address Input M1, M2 Read Protocol Mode Pins ( M1=VSS, M2=VDD ) DQn Bi-directional Data Bus G Asynchronous Output Enable SW Synchronous Global Write Enable SS Synchronous Select SWa Synchronous Byte a Write Enable TCK JTAG Test Clock SWb Synchronous Byte b Write Enable TMS JTAG Test Mode Select SWc Synchronous Byte c Write Enable TDI JTAG Test Data Input SWd Synchronous Byte d Write Enable TDO JTAG Test Data Output ZZ Asynchronous Power Down VSS GND VDD Core Power Supply NC No Connection 128Kx36 & 256Kx18 Synchronous Pipelined SRAM FEATURES • 128Kx36 or 256Kx18 Organizations. • 3.3V Core Power Supply. • LVTTL Input and Output Levels. • Differential, PECL Clock Inputs K, K. • Synchronous Read and Write Operation • Registered Input and Registered Output • Internal Pipeline Latches to Support Late Write. • Byte Write Capability(four byte write selects, one for each 9bits) • Synchronous or Asynchronous Output Enable. • Power Down Mode via ZZ Signal. • JTAG 1149.1 Compatible Test Access port. • 119(7x17)Pin Ball Grid Array Package(14mmx22mm) Organization Part Number Cycle Time Access Time 128Kx36 K7P403622M-H20 5 2.5 K7P403622M-H16 6 3.0 K7P403622M-H19 7 3.5 256Kx18 K7P401822M-H20 5 2.5 K7P401822M-H16 6 3.0 K7P401822M-H19 7 3.5 FUNCTIONAL BLOCK DIAGRAM SA[0:16] or SA[0:17] CK SS SW SWx G 128Kx36 Data In ZZ DQx[1:9] (x=a, b, c, d) or (x=a, b) (x=a, b, c, d) or (x=a, b) K K CK or 256Kx18 Array Column Decoder Write/Read Circuit Register 0 1 Data Out Register 1 Read Address Register Write Address Register Latch SW Register SW Register Latch SWx Register SWx Register SS Register SS Register 0 |
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