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K4C560838C-TCD3 Datasheet(PDF) 4 Page - Samsung semiconductor

Part # K4C560838C-TCD3
Description  256Mb Network-DRAM
Download  42 Pages
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Manufacturer  SAMSUNG [Samsung semiconductor]
Direct Link  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

K4C560838C-TCD3 Datasheet(HTML) 4 Page - Samsung semiconductor

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K4C5608/1638C
256Mb Network-DRAM
REV. 0.7 Aug. 2003
- 4 -
• Fully Synchronous Operation
Double Data Rate (DDR)
Data input/output are synchronized with both edges of DQS.
Differential Clock (CK and CK)inputs
CS, FN and all address input signals are sampled on the positive edge of CK.
Output data (DQs and DQS) is referenced to the crossings of CK and CK.
• Fast clock cycle time of 5ns minimum
Clock : 200MHz maximum
Data : 400Mbps/pin maximum
• Quad independent banks operation
• Fast cycle and short Iatency
• Bidirectional data strobe signal
• Distributed Auto-Refresh cycle in 7.8us
• Self-Refresh
• Power Down Mode
• Variable Write Length Control
• Write Latency = CAS Latency - 1
• Programmable CAS Latency and Burst Length
CAS Latency = 3, 4
Burst Length = 2, 4
• Organization K4C561638C-TC : 4,194,304 words x4 banks x 16
K4C560838C-TC : 8,388,608 words x4 banks x 8
• Power supply voltage Vdd : 2.5 ± 0.15V
VddQ : 2.5 ± 0.15V
• 2.5V CMOS I/O comply with SSTL-2 (Strong / Normal / Weaker / Weakest)
• Package 400X875mil, 66pin TSOP II, 0.65mm pin pitch (TSOP II 66-P-400-0.65)
Item
K4C560838/1638C-TC
D4 (400Mbps)
DA (366Mbps)
D3 (333Mbps)
tCK Clock Cycle Time (Min.)
CL=3
5.5ns
6ns
6.5ns
CL=4
5ns
5.5ns
6ns
tRC Random Read/Write Cycle Time (Min.)
25ns
27.5ns
30ns
tRAC Random Access Time (Max.)
22ns
24ns
26ns
IDD1S Operating Current (Single bank) (Max.)
310mA
300mA
290mA
IDD2P Power Down Current (Max.)
2mA
2mA
2mA
IDD6 Self-Refresh Current(Max.)
3mA
3mA
3mA
Key Feature


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