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S6B1713A15-XXX0 Datasheet(PDF) 25 Page - Samsung semiconductor |
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S6B1713A15-XXX0 Datasheet(HTML) 25 Page - Samsung semiconductor |
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25 / 70 page  S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD 21 LCD DISPLAY CIRCUITS Oscillator This is completely on-chip oscillator and its frequency is nearly independent of VDD. This oscillator signal is used in the voltage converter and display timing generation circuit. * Test condition: Temperature: 25 °C & 85°C, TEMPS=”L”, No load VDD vs. fosc 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 2.4 2.7 3.0 3.3 3.6 4.0 4.5 5.0 5.5 VDD [V] fosc [kHz] 1/33 Duty (25캜 ) 1/49 Duty (25캜 ) 1/65 Duty (25캜 ) 1/33 Duty (85캜 ) 1/49 Duty (85캜 ) 1/65 Duty (85캜 ) Figure 13. VDD vs. fOSC Display Timing Generator Circuit This circuit generates some signals to be used for displaying LCD. The display clock, CL, generated by oscillation clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip RAM is generated in synchronization with the display clock (CL) and the 132-bit display data is latched by the display data latch circuit in synchronization with the display clock. The display data, which is read to the LCD driver, is completely independent of the access to the display data RAM from the microprocessor. The display clock generates an LCD AC signal(M) which enables the LCD driver to make a AC drive waveform, and also generates an internal common timing signal and start signal to the common driver. Driving 2-frame AC driver waveform and internal timing signal are shown in figure 14. In a multiple-chip configuration, the slave chip requires the M, CL and DISP signals from the master. Table 11 shows the M, CL, and DISP status. Table 11. Master and Slave Timing Signal Status Operation mode Oscillator M CL DISP ON (internal clock used) Output Output Output Master OFF (external clock used) Output Input Output Slave - Input Input Input |
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