263 / 256 CHANNEL TFT-LCD GATE DRIVER

S6C0657

7

PIN DESCRIPTIONS

Symbol

Pin Name

I / O

Description

DI/O

DO/I

Start pulse input/output

I / O

When these inputs operate as the input, the start pulse data is

read at the rising edge of shift clock, CPV.

When these inputs operate as the output, the start pulse output

is the next chip’s start pulse input. The output pulse is

generated

at the falling edge of the 263th shift clock, CPV.

When U/D = H, the shift register does right shifting operation.

(Input = DI/O and output = DO/I)

When U/D = L, the shift register does left shifting operation.

(Input = DO/I and output = DI/O)

U/D

Shift direction control input

I

When U/D = H, DI/O

→ G001 →……→ G263 → DO/I

When U/D = L, DO/I

→ G263 →……→ G001 → DI/O

CPV

Shift clock input

I

The shift register operates in synchronization with the rising

edge of this input

SEL

Output selection input

I

This input selects the number of available outputs

When SEL = H, 263 output mode

When SEL = L, 256 output mode(G129 - G135 are disabled)

OE

Output enable input

I

This input controls the state of the driver outputs.

When OE = H, the driver output is fixed to VOFF.

When OE = L, the driver output is VGG or VOFF corresponding

to the data.

G001

to

G263

Driver output

O

The output signals change in synchronization with the rising

edge of shift clock input, CPV.

The amplitude of the driver output is VGG - VOFF.

VOFF

Negative power supply

I

This input is logic and driver ground.

Always, has negative potential.

VLO

Logic input low voltage

I

This input operates as the reference to the level conversion of

the other input.

The other logic input range: VDD - VLO

VGG

Driver positive power supply

I

6 to 33 V

The TFT gate ON voltage is VGG - VOFF.

VDD

Logic positive power supply

I

2.7 to 5.5 V