S6A0065

40 CH SEGMENT/COMMON DRIVER FOR DOT MATRIX LCD

8

AC Characteristics(V

Characteristic

Symbol

Test condition

Min

Max

Unit

Applicable pin

Data Shift Frequency

f

CL

-

-

400

kHz

CL2

Clock High Level Width

t

WCKH

-

800

-

CL1, CL2

Clock Low Level Width

t

WCKL

-

800

-

CL2

Clock Set-up Time

t

SL

from CL2 to CL1

500

-

ns

t

LS

from CL1 to CL2

500

-

CL1, CL2

Clock Rise/Fall Time

t

-

-

200

Data Set-up Time

t

SU

-

300

-

DL1, DL2, DR1,

DR2, FLM

Data Hold Time

t

DH

-

300

-

Data Delay Time

t

D

C

-

500

DL1, DL2,

DR1, DR2

* Input/Output current is excluded; When input is at the intermediate level with CMOS, excessive current flows

through the input circuit to the power supply, To avoid this, input level must be fixed at "H" or "L".