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S524C20D10 Datasheet(PDF) 7 Page - Samsung semiconductor |
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S524C20D10 Datasheet(HTML) 7 Page - Samsung semiconductor |
7 / 22 page DATA SHEET S524C20D10/20D20/80D40/80D80 SERIAL EEPROM 4-7 Master SCL Line Data from Transmitter ACK ACK from Receiver Bit 9 Bit 1 Figure 4-8. Acknowledge Response From Receiver • Slave Address: After the master initiates a Start condition, it must output the address of the device to be accessed. The most significant four bits of the slave address are called the “device identifier”. The identifier for the S524C20D10/20D20/80D40/80D80 is “1010B”. The next three bits comprise the address of a specific device. The device address is defined by the state of the A0, A1 and A2 pins. Using this addressing scheme, you can cascade up to eight S524C20D10/20D20 or four S524C80D40 or two for S524C80D80 on the bus (see Table 4-2 below). The b1 for S524C80D40 or the b1, b2 for S524C80D80 are used by the master to select which of the blocks of internal memory (1 block = 256 words) are to be accessed. The bits are in effect the most significant bit of the word address. • Read/Write: The final (eighth) bit of the slave address defines the type of operation to be performed. If the R/W bit is “1”, a read operation is executed. If it is “0”, a write operation is executed. Table 4-2. Slave Device Addressing Function Device Identifier Device Address R/W Bit b7 b6 b5 b4 b3 b2(note) b1(note) b0 Read 1 0 1 0 A2 A1 A0 1 Write 1 0 1 0 A2 A1 A0 0 Write-protect 0 1 1 0 A2 A1 A0 0 NOTE: The b1 for the S524C80D40 or the b2, b1 for the S524C80D80 correspond to the MSB of the memory array address word. |
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