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S524AB0XB1 Datasheet(PDF) 5 Page - Samsung semiconductor |
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S524AB0XB1 Datasheet(HTML) 5 Page - Samsung semiconductor |
5 / 16 page DATA SHEET S524AB0X91/B0XB1 SERIAL EEPROM 6-5 FUNCTION DESCRIPTION I 2C-BUS INTERFACE The S524AB0X91/B0XB1 supports the I 2C-bus serial interface data transmission protocol. The two-wire bus consists of a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected to V CC by a pull-up resistor that is located somewhere on the bus. Any device that puts data onto the bus is defined as a “transmitter” and any device that gets data from the bus is a “receiver.” The bus is controlled by a master device whic h generates the serial clock and start/stop conditions, controlling bus access. Using the A0, A1, and A2 input pins, up to eight S524AB0X91/B0XB1 devices can be connected to the same I 2C-bus as slaves (see Figure 6-6). Both the master and slaves can operate as a transmitter or a receiver, but the master device determines which bus operating mode would be active. SDA Bus Master (Transmitter/ Receiver) MCU S524AB0X91/ B0XB1 Tx/Rx A0 A1 A2 Slave 1 To VCC or VSS S524AB0X91/ B0XB1 Tx/Rx A0 A1 A2 Slave 2 To VCC or VSS S524AB0X91/ B0XB1 Tx/Rx A0 A1 A2 Slave 3 To VCC or VSS S524AB0X91/ B0XB1 Tx/Rx A0 A1 A2 Slave 8 To VCC or VSS R VCC R VCC SCL Figure 6-6. Typical Configuration |
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