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S524A40X10 Datasheet(PDF) 5 Page - Samsung semiconductor

Part No. S524A40X10
Description  1K/2K/4K-bit Serial EEPROM for Low Power with software write protect
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Maker  SAMSUNG [Samsung semiconductor]
Homepage  http://www.samsung.com/Products/Semiconductor
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DATA SHEET
S524A40X10/40X20/40X40 SERIAL EEPROM
2-5
FUNCTION DESCRIPTION
I
2C-BUS INTERFACE
The S524A40X10/40X20/40X40 supports the I
2C-bus serial interface data transmission protocol. The two-wire bus
consists of a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected
to V
CC by a pull-up resistor that is located somewhere on the bus.
Any device that puts data onto the bus is defined as the “transmitter” and any device that gets data from the bus
is the “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop
conditions, controlling bus access. Using the A0,A1 and A2 input pins, up to eight S524A40X10/40X20 (four for
S524A40X40) devices can be connected to the same I
2C-bus as slaves (see Figure 2-6). Both the master and
slaves can operate as transmitter or receiver, but the master device determines which bus operating mode would
be active.
SDA
Bus Master
(Transmitter/
Receiver)
MCU
S524A40X20
Tx/Rx
A0 A1 A2
Slave 1
To VCC or VSS
S524A40X20
Tx/Rx
A0 A1 A2
Slave 2
To VCC or VSS
S524A40X20
Tx/Rx
A0 A1 A2
Slave 3
To VCC or VSS
S524A40X20
Tx/Rx
A0 A1 A2
Slave 8
To VCC or VSS
R
VCC
R
VCC
SCL
NOTE: The A0 does not affect the device address of the S524A40X40.
Figure 2-6. Typical Configuration (16 Kbits of Memory on the I
2C-Bus)




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