PRODUCT OVERVIEW

S3C72B5/C72B7/C72B9/P72B9

1-6

POWER DOWN

To reduce power consumption, there are two power-down modes: idle and stop. The IDLE instruction initiates idle

mode and the STOP instruction initiates stop mode.

In idle mode, only the CPU clock stops while peripherals and the oscillation source continue to operate normally.

Stop mode effects only the main system clock — a subsystem clock, if used, continues oscillating. In stop mode,

main system clock oscillation stops completely, halting all operations except for a few basic peripheral functions.

RESET or an interrupt can be used to terminate either idle or stop mode.

RESET

RESET

When a

RESET signal occurs during normal operation or during power-down mode, the CPU enters idle mode

when the reset operation is initiated. When the standard oscillation stabilization interval (31.3 ms at 4.19 MHz)

has elapsed, normal CPU operation resumes.

I/O PORTS

The S3C72B5/C72B7/C72B9 has 13 I/O ports. Pin addresses for all I/O ports are mapped in bank 15 of the RAM.

There are 4 input pins and 47 configurable I/O pins for a total of 51 I/O pins. The contents of I/O port pin latches

can be read, written, or tested at the corresponding address using bit manipulation instructions.

TIMERS and TIMER/COUNTERS

The timer function has four main components: an 8-bit basic interval timer, an 8-bit timer/counter, a 16-bit

timer/counter and a watch timer. The 8-bit basic timer generates interrupt requests at precise intervals, based on

the selected clock frequency and has watch-dog timer function.

The programmable 8-bit and 16-bit timer/counters are used for external event counting, generation of arbitrary

clock frequencies for output, and dividing external clock signals. The 16-bit timer/counter is the source of the

clock signal that is required to drive the serial I/O interface and configurable as two 8-bit timer/counters.

The watch timer has an 8-bit watch timer mode register, a clock selector and a frequency divider circuit. Its

functions include real-time and watch-time measurement, clock generation for the LCD controller and frequency

outputs for buzzer sound.

LCD DRIVER/CONTROLLER

The S3C72B5/C72B7/C72B9 can directly drive an up-to-1,280-dot LCD panel. The LCD function block has the

following components:

— RAM area for storing display data

— 80 segment output pins (SEG0–SEG79)

— Segment expandable circuit

— 16 common output pins (COM0–COM15)

— 5 operating power supply pins (V

— Sixteen level LCD contrast control circuit (software)

Frame frequency, LCD clock, duty, and segment pins used for display output are controlled by bit settings in the

8-bit mode register, LMOD. You use the 4-bit LCD control register, LCON, to turn the LCD display on and off,

and to control current supplied to the dividing resistors. Segment data are output using a direct memory access

method synchronized with the LCD frame frequency (f

Using the main system clock, the LCD panel operates in idle mode; during stop mode, it is turned off. If a

subsystem clock is used as a clock source, the LCD panel will continue to operate during stop and idle modes.