S3C72C8 datasheet(7/37 Pages) SAMSUNG

Part #	S3C72C8

Description	The S3C72C8 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Arrangeable M

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Manufacturer	SAMSUNG [Samsung semiconductor]

Direct Link	http://www.samsung.com/Products/Semiconductor

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S3C72C8/P72C8

PRODUCT OVERVIEW

1-7

Table 1-1. S3C72C8 Pin Descriptions (Continued)

Pin Name

Type

Description

Circuit

Type

Number

Share Pin

SEG0-SEG3

I/O

LCD segment display signal output pins

H–13

19-22

(25-28)

P5.0-P5.3

SEG4-SEG7

23-26

(29-32)

P6.0-P6.3

SEG8-SEG11

27-30

(33-36)

P7.0-P7.3

SEG12-SEG15

O

LCD segment display output pins

H–6

31-34

(37-40)

COM7-COM4

COM0-COM3

O

LCD common signal output pins

H–4

38-35

(2-1,

42-41)

–

COM4-COM7

I/O

LCD common signal output pins

H–6

34-31

(40-37)

SEG12–

SEG15

SCK

I/O

Serial interface clock signal

E–1

16 (22)

P0.0

SO

I/O

Serial data output

E–1

15 (21)

P0.1

SI

I/O

Serial data input

E–1

14 (20)

P0.2

BTCO

I/O

Basic timer overflow signal

E–1

13 (19)

P0.3

TCLO1

I/O

Timer/counter external clock output

E–1

39 (3)

P1.0/INT0

TCL1

I/O

Timer/counter external clock input

E–1

40 (4)

P1.1/INT1

CLO

I/O

Clock output

E–1

41 (5)

P1.2/INT2

BUZ

I/O

Frequency output to buzzer

E–1

42 (6)

P1.3/INT4

RESET

I

System

RESET pin

B

12 (18)

–

Xin, Xout

–

Clock input and output pins for main system

clock

–

8-7

(14-13)

–

XTin, XTout

–

Clock input and output pins for subsystem

clock

–

10-11

(16-17)

–

CIN0–CIN3

I

Analog input port for Comparator

F–8

1-4

(7-10)

P2.0/K0

-P2.3/K3

K0–K3

I/O

External interrupts. The triggering edge is

selectable.

F–8

1-4

(7-10)

P2.0/CIN0

-P2.3/CIN3

INT0

INT1

I

External interrupts. The triggering edge for

INT0 and INT1 is selectable.

E–1

39 (3)

40 (4)

P1.0/TCLO1

-P1.1/TCL1

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S3C72C8 Datasheet(PDF) 7 Page - Samsung semiconductor

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