S3C72B5/C72B7/C72B9/P72B9

PRODUCT OVERVIEW

1-11

Table 1-1. S3C72B5/C72B7/C72B9 Pin Descriptions (Continued)

Pin Name

Pin Type

Description

Number

Share Pin

INT0

I

External interrupts with rising/falling edge detection

28

P1.0

INT1

I

External interrupts with rising/falling edge detection

29

P1.1

INT2

I

External quasi-interrupts with rising/falling edge

detection

30

P1.2

INT4

I

External interrupts with rising/falling edge detection

31

P1.3

M

I/O

Alternated signal for SEG driver

32

P2.0

LCDFR

I/O

Synchronous frame signal for SEG driver

33

P2.1

CLO1

I/O

Clock output or operating clock for SEG driver

34

P2.2

CLO2

I/O

Clock output or operating clock for SEG driver

35

P2.3

CL

I/O

Data shift clock for SEG driver

36

P3.0

TCLO0

I/O

Timer/counter0 clock output

36

P3.0

TCLO1

I/O

Timer/counter1 clock output

37

P3.1

TCL0

I/O

External clock input for timer/counter 0

38

P3.2

TCL1

I/O

External clock input for timer/counter 1

39

P3.3

CIN0–CIN2

I/O

CIN0,1: comparator input only

CIN2: comparator input or external reference input

40, 41

42

P4.0–P4.1

P4.2

SEG0–SEG47

O

LCD segment data output

122–75

–

SEG48–

SEG79

O

LCD segment data output

74–43

Port13–6

SEG80–

SEG87

O

LCD segment data output

2,1,

128–123

COM15–8

COM0–COM7

O

LCD common data output

10–3

–

COM8–COM15

O

LCD common data output

123–128

1, 2

SEG87–80

–

LCD power supply. Voltage dividing resistors are

fixed.

15–11

–

–

Main power supply

20

–

–

Ground

21

–

–

Crystal, Ceramic, or RC oscillator signal I/O for main

system clock.

23, 22

–

–

Crystal oscillator signal I/O for subsystem clock.

25, 26

–

TEST

I

24

–

RESET

I

Reset signal

27

–

NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.