S3C7048 datasheet(11/38 Pages) SAMSUNG

Part #	S3C7048

Description	The S3C7044/C7048 single-chip CMOS microcontroller has been designed for very high-performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Ar

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Manufacturer	SAMSUNG [Samsung semiconductor]

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S3C7044/C7048/P7048

PRODUCT OVERVIEW

1-11

Table 1-1. S3C7044/C7048 Pin Descriptions (Continued)

Pin Name

Pin Type

Description

Number

Share

SCK

I/O

Serial I/O interface clock signal

12 (28)

P0.0

SO

I/O

Serial data output

11 (27)

P0.1

SI

I/O

Serial data input

10 (26)

P0.2

BTCO

I/O

Basic timer clock output (2 Hz, 16 Hz, 64 Hz, or 256

Hz at 4.19 MHz)

9 (25)

P0.3

INT0, INT1

I

External interrupts. The triggering edge for INT0 and

INT1 is selectable. INT0 is synchronized to system

clock.

4, 3

(20, 19)

P1.0, P1.1

INT2

I

Quasi-interrupt with detection of rising edges

2 (18)

P1.2

INT4

I

External interrupt with detection of rising and falling

edges.

1 (17)

P1.3

TCLO0

I/O

Timer/counter 0 clock output

8 (24)

P2.0

TCLO1

I/O

Timer/counter 1 clock output

7 (23)

P2.1

CLO

I/O

Clock output

6 (22)

P2.2

BUZ

I/O

2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at

4.19 MHz for buzzer sound

5 (21)

P2.3

TCL0

I/O

External clock input for timer/counter 0

20 (38)

P3.0

TCL1

I/O

External clock input for timer/counter 1

19 (37)

P3.1

KS0–KS3

KS4–KS7

I/O

Quasi-interrupt inputs with falling edge detection

37–34

(11–8)

41–38

(15–12)

P6.0–P6.3

P7.0–P7.3

VDD

–

Power supply

21 (39)

–

VSS

–

Ground

42 (16)

–

RESET

I

Reset signal

31 (5)

–

Xin, Xout

–

Crystal, ceramic, or RC oscillator signal for system

clock (For external clock input, use Xin and input

Xin's reverse phase to Xout)

33, 32

(7, 6)

–

TEST

–

Test signal input (must be connected to VSS)

22 (40)

–

NC

–

No connection (must be connected to VSS)

(33, 34)

–

NOTE: Parentheses indicate pin number for 44 QFP package.

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