KS8620

1 Chip CODEC for Digital Answering phone

PIN DESCRIPTION

Pin No

Symbol

Description

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

V

BB

VF

V

CC

CLKSEL

PDN

VF

VF

Analog ground

Analog output of the receiver filter

Receive frame sync pulse. 8KHz pulse train.

PCM data input

Logic input which selects either 1.536MHz / 1.544MHz or 2.048MHz for master

clock in normal operation and BCLKx is used for both TX and RX directions.

Alternately direct clock input available, vary from 64KHz to 2.048MHz.

Normally connected continuously low, MCLKx is selected for all DAC timing.

Alternately direct 1.536MHz / 1.544MHz or 2.048MHz clock input is available.

1.536MHz / 1.544MHz or 2.048MHz clock input is available

May be vary from 64KHz 2.048MHz, but BCLKx is externally tied with MCLKx

in normal operation.

PCM data output.

TX frame sync pulse. 8KHz pulse train.

Changed from high to low during the encoder timeslot. Open drain output.

Analog output of the TX input amplifier.

Used to set gain through external resistor between pin 14 to pin 15.

Inverting input stage of the TX analog signal.

Non-inverting input stage of the TX analog signal.

Characteristic

Positive Supply Voltage

Negative Supply Voltage

Voltage at any Analog Input or Output

Voltage at any Digital Input or Output

Operating Temperature Range

Storage Temperature Range

Lead Temperature Range ( soldering , 10 sec )

Symbol

Value

Unit

Vcc

Ta

+7

-7

Vcc + 0.3 to VBB - 0.3

Vcc + 0.3 to GNDA - 0.3

0 to 70

-65 to +150

300

V

V

V

V