KM416S8030

CMOS SDRAM

REV. 2 Mar. '98

Preliminary

The KM416S8030 is 134,217,728 bits synchronous high data

rate Dynamic RAM organized as 4 x 2,097,152 words by 16

bits, fabricated with SAMSUNG

′s high performance CMOS

technology. Synchronous design allows precise cycle control

with the use of system clock I/O transactions are possible on

every clcok cycle. Range of operating frequencies, programma-

ble burst length and programmable latencies allow the same

device to be useful for a variety of high bandwidth, high perfor-

mance memory system applications.

• JEDEC standard 3.3V power supply

• LVTTL compatible with multiplexed address

• Four banks operation

• MRS cycle with address key programs

-. CAS Latency (2 & 3)

-. Burst Length (1, 2, 4, 8 & full page)

-. Burst Type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system

clock.

• Burst Read Single-bit Write operation

• DQM for masking

• Auto & self refresh

• 64ms refresh period (4K cycle)

GENERAL DESCRIPTION

FEATURES

FUNCTIONAL BLOCK DIAGRAM

2M x 16Bit x 4 Banks Synchronous DRAM

ORDERING INFORMATION

Part NO.

MAX Freq.

Interface Package

KM416S8030T-G/F8

125MHz

LVTTL

54pin

TSOP(II)

KM416S8030T-G/FH

100MHz

KM416S8030T-G/FL

100MHz

KM416S8030T-G/F10

100MHz

Samsung Electronics reserves the right to

change products or specification without

notice.

*

Bank Select

Data Input Register

2M x 16

2M x 16

Column Decoder

Latency & Burst Length

Programming Register

LCKE

LRAS

LCBR

LWE

LDQM

CLK

CKE

CS

RAS

CAS

WE

LDQM

LWE

LDQM

DQi

CLK

ADD

LCAS

LWCBR

2M x 16

2M x 16

Timing Register

UDQM