KM4132G271B datasheet(5/51 Pages) SAMSUNG

Part #	KM4132G271B

Description	128K x 32bit x 2 Banks Synchronous Graphic RAM LVTTL

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Manufacturer	SAMSUNG [Samsung semiconductor]

Direct Link	http://www.samsung.com/Products/Semiconductor

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KM4132G271B

CMOS SGRAM

- 5 -

Rev. 2.4 (May 1998)

PIN CONFIGURATION DESCRIPTION

NAME

INPUT FUNCTION

CLK

System Clock

Active on the positive going edge to sample all inputs.

CS

Chip Select

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQMi

CKE

Clock Enable

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one clock +tSS prior to new command.

Disable input buffers for power down in standby.

A0 ~ A8

Address

Row / Column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA8, Column address : CA0 ~ CA7

A9(BA)

Bank Select Address

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

RAS

Row Address Strobe

Latches row addresses on the positive going edge of the CLK withRAS low.

Enables row access & precharge.

CAS

Column Address Strobe

Latches column addresses on the positive going edge of the CLK withCAS low.

Enables column access.

WE

Write Enable

Enables write operation and Row precharge.

DQMi

Data Input/Output Mask

Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when DQM active.(Byte Masking)

DQi

Data Input/Output

Data inputs/outputs are multiplexed on the same pins.

DSF

Define Special Function

Enables write per bit, block write and special mode register set.

VDD/VSS

Power Supply /Ground

Power Supply : +3.3V

±0.3V/Ground

VDDQ /VSSQ

Data Output Power /Ground

Provide isolated Power/Ground to DQs for improved noise immunity.

N.C

No Connection

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KM4132G271B Datasheet(PDF) 5 Page - Samsung semiconductor

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