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K4S643232E Datasheet(PDF) 3 Page - Samsung semiconductor |
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K4S643232E Datasheet(HTML) 3 Page - Samsung semiconductor |
3 / 12 page K4S643232E-TE/N CMOS SDRAM - 3 - Rev. 1.4 (Dec. 2001) The K4S643232E is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabricated with SAMSUNG ′s high performance CMOS technol- ogy. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. • 3.3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock • Burst read single-bit write operation • DQM for masking • Auto & self refresh • 15.6us refresh duty cycle(4K/64ms) • Extended Temperature range : -25oC to +85oC GENERAL DESCRIPTION FEATURES 512K x 32Bit x 4 Banks Synchronous DRAM ORDERING INFORMATION • - E/N : Extended temperature (-25oC - 85oC) Part NO. Max Freq. Interface Package K4S643232E-TE/N50 200MHz LVTTL 86 TSOP(II) K4S643232E-TE/N60 166MHz K4S643232E-TE/N70 143MHz FUNCTIONAL BLOCK DIAGRAM Samsung Electronics reserves the right to change products or specification without notice. * Bank Select Data Input Register 512K x 32 512K x 32 Column Decoder Latency & Burst Length Programming Register LCKE LRAS LCBR LWE LDQM CLK CKE CS RAS CAS WE DQM LWE LDQM DQi CLK ADD LCAS LWCBR 512K x 32 512K x 32 Timing Register |
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