K4S643232E-TE50 datasheet(9/12 Pages) SAMSUNG

Part #	K4S643232E-TE50

Description	2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL(3.3V)

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Manufacturer	SAMSUNG [Samsung semiconductor]

Direct Link	http://www.samsung.com/Products/Semiconductor

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K4S643232E-TE/N

CMOS SDRAM

- 9 -

Rev. 1.4 (Dec. 2001)

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf)=1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

Note :

Parameter

Symbol

Version

Unit

-50

-60

-70

Row active to row active delay

tRRD(min)

10

12

14

ns

RAS to CAS delay

tRCD(min)

15

18

20

ns

Row precharge time

tRP(min)

15

18

20

ns

Row active time

tRAS(min)

40

42

49

ns

tRAS(max)

100

us

Row cycle time

tRC(min)

55

60

70

ns

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

Parameter

Symbol

-50

-60

-70

Unit

Note

Min

Max

Min

Max

Min

Max

CLK cycle time

CAS Latency=3

tCC

5

1000

6

1000

7

1000

ns

1

CAS Latency=2

10

CLK to valid

output delay

CAS Latency=3

tSAC

-

4.5

-

5.5

-

5.5

ns

1, 2

CAS Latency=2

-

6

-

6

-

6

Output data hold time

tOH

2

-

2

-

2

-

ns

2

CLK high pulse width

CAS Latency=3

tCH

2

-

2.5

-

3

-

ns

3

CAS Latency=2

3

-

3

-

3

-

CLK low

pulse width

CAS Latency=3

tCL

2

-

2.5

-

3

-

ns

3

CAS Latency=2

3

-

3

-

3

-

Input setup time

CAS Latency=3

tSS

1.5

-

1.5

-

1.75

-

ns

3

CAS Latency=2

2.5

-

2.5

-

2.5

-

Input hold time

tSH

1

-

1

-

1

-

ns

3

CLK to output in Low-Z

tSLZ

1

-

1

-

1

-

ns

2

CLK to output

in Hi-Z

CAS Latency=3

tSHZ

-

4.5

-

5.5

-

5.5

ns

-

CAS Latency=2

-

6

-

6

-

6

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