SDRAM 256Mb E-die (x4, x8, x16)

CMOS SDRAM

Rev. 1.5 May 2004

SDRAM 256Mb E-die (x4, x8, x16)

Part No.

Orgainization

Max Freq.

Interface

Package

K4S560432E-TC(L)75

64M x 4

133MHz (CL=3)

LVTTL

54pin TSOP(II)

K4S560832E-TC(L)75

32M x 8

133MHz (CL=3)

K4S561632E-TC(L)60/75

16M x 16

166MHz (CL=3)

The K4S560432E / K4S560832E / K4S561632E is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x

16,777,216 words by 4 bits / 4 x 8,388,608 words by 8bits / 4 x 4,194,304 words by 16bits, fabricated with SAMSUNG's high perfor-

mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible

on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to

be useful for a variety of high bandwidth, high performance memory system applications.

• JEDEC standard 3.3V power supply

• LVTTL compatible with multiplexed address

• Four banks operation

• MRS cycle with address key programs

-. CAS latency (2 & 3)

-. Burst length (1, 2, 4, 8 & Full page)

-. Burst type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system clock.

• Burst read single-bit write operation

• DQM (x4,x8) & L(U)DQM (x16) for masking

• Auto & self refresh

• 64ms refresh period (8K Cycle)

GENERAL DESCRIPTION

FEATURES

16M x 4Bit x 4 Banks / 8M x 8Bit x 4 Banks / 4M x 16Bit x 4 Banks SDRAM

Ordering Information

Row & Column address configuration

Organization

Row Address

Column Address

64Mx4

A0~A12

A0-A9, A11

32Mx8

A0~A12

A0-A9

16Mx16

A0~A12

A0-A8