K4E170411D, K4E160411D

CMOS DRAM

K4E170412D, K4E160412D

NOTES

An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles

before proper device operation is achieved.

Measured with a load equivalent to 2 TTL(5V)/1 TTL(3.3V) loads and 100pF.

Operation within the

If

Assumes that

teristics only. If

tion of the cycle. If

data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition

of the data out is indeterminate.

Either

These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle

and read-modify-write cycles.

Operation within the

These specifications are applied in the test mode.

In test mode read cycle, the value of

should be specified in test mode cycles by adding the above value to the specified value in this data sheet.

If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes

high before RAS high going, the open circuit condition of the output is achieved by RAS high going.

If

For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/2048(2K) cycles of burst refresh must be exe-

cuted within 64ms/32ms before and after self refresh, in order to meet refresh specification.

For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immedi-

ately before and after self refresh in order to meet refresh specification.

5.

6.

7.

8.

9.

10.

11.

12.

13.

14.

15.

16.

1.

2.

3.

4.

17.