5

Standard ICs

BU9728AKV

CS

SCK

SD

C / D

Fig.1 Interface timing

SCK

SD

D7

D6

D0

D7

Fig.2 Command cycle

Serial data is 4-line data transmitted in synchronization with the clock. Serial data with a bit length of 8 bits is input in

synchronization with SCK. If C / D is HIGH at the rising edge of the 8

× nth SCK clock pulse, the serial data is recog-

nized as command data, and if C / D is LOW, the serial data is recognized as display data. Serial data is input in

sequential order, starting from the MSB.