10

Memory ICs

BR93LL46F / BR93LL46FV

CS

SK

DI

DO

D1

D0

READY

BUSY

Write command

Status detection

Command input

DI

DO

D1

D0

BUSY

READY

High-Z

High-Z

Fig. 9 Timing diagram chart

4) When the

µ-COM port is the open drain port

When the

µ-COM port is the open drain output port, it

responds through software as shown in Figure 8. This

method will not work during CMOS input and output.

The timing which becomes a problem (production of

feedthrough current paths) for the open drain port only

occurs when CS is HIGH after a write command. Feed-

through current paths can occur in the period between

the rise of the CS to the input of the start bit. If CS rises

before the start bit, as shown in Figure 8, and DI is

HIGH at the same time, current paths are not created.

Make sure to set SK to LOW during a CS rise.

In this case, however, the first SK rise after the CS

rises is interpreted as the start bit. Therefore, caution is

required. Figure 9 shows a timing chart from the end of

a write command to the next command input. As

shown in the figure, after completion of the write com-

mand input, when CS rises, set SK to LOW and stop

the SK input. Otherwise, if DO is HIGH when a clock

pulse is input, this is taken as the start bit and may

cause erroneous operation.

Start bit

1

2

34

CS

SK

DI

DO

High-Z

Fig. 8 Using an open drain port