BR93LC46-W / BR93LC46F-W / BR93LC46RF-W /

Memory ICs

BR93LC46FJ-W / BR93LC46RFJ-W / BR93LC46FV-W

(3) Timing chart

CS

SK

DI

DO (READ)

DO (WRITE)

STATUS VALID

Fig.9 Synchronized data timing

a write command and before the output of the next command start bit. Also, DO must be in a HIGH-Z state when CS is LOW.

(4) Reading (Fig.10)

When the read command is acknowledged, the data (16 bits) for the input address is output serially. The data is

synchronized with the SK rise during A0 acquisition and a “0” (dummy bit) is output. All further data is output in

synchronization with the SK pulse rises.

CS

SK

DI

DO

(

(

D14

D15

D1

D14

D15

0

High Z

11

0

A5

A4

A1

A0

1

2

4

9

10

25

26

D0

(

this function, if the SK clock is input following execution of one of the above reading commands, data is read from upper addresses in succession.

CS is held in HIGH state during automatic incrementing.

(

"1" is recognized as the start bit, and subsequent operation commences. This applies also to all commands described subsequently.

Fig.10 Read cycle timing (READ)